quasiSoC
No-MMU Linux capable RISC-V SoC designed to be useful. (by regymm)
RISCV
A Pipelined RISC-V RV32I Core in Verilog [Moved to: https://github.com/georgeyhere/Toast-RV32i] (by georgeyhere)
| quasiSoC | RISCV | |
|---|---|---|
| 1 | 1 | |
| 91 | 11 | |
| - | - | |
| 6.4 | 8.8 | |
| 10 days ago | over 2 years ago | |
| C | C | |
| GNU General Public License v3.0 only | - |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
quasiSoC
Posts with mentions or reviews of quasiSoC.
We have used some of these posts to build our list of alternatives
and similar projects.
RISCV
Posts with mentions or reviews of RISCV.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-06-22.
-
Novice needs help with RISC-V toolchain
To this end, I wrote a testbench that encodes instructions and places them into a text file using SV structs. Is there any tool that can decode the output to Assembly instructions to check that the testbench is working? Or even better, is there some way to generate hex/binary code from Assembly? I have manually converted some instructions to binary and am reasonably sure the code works but am not 100% sure.
What are some alternatives?
When comparing quasiSoC and RISCV you can also consider the following projects:
spu32 - Small Processing Unit 32: A compact RV32I CPU written in Verilog
Toast-RV32i - Pipelined RISC-V RV32I Core in Verilog
bronzebeard - Minimal assembler and ecosystem for bare-metal RISC-V development
chipyard - An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
NyuziProcessor - GPGPU microprocessor architecture
RVVM - The RISC-V Virtual Machine
openwifi - open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software
rt-thread - RT-Thread is an open source IoT real-time operating system (RTOS).