Novice needs help with RISC-V toolchain

• RISCV

  1 11 8.8 C

  Discontinued A Pipelined RISC-V RV32I Core in Verilog [Moved to: https://github.com/georgeyhere/Toast-RV32i] (by georgeyhere)

To this end, I wrote a testbench that encodes instructions and places them into a text file using SV structs. Is there any tool that can decode the output to Assembly instructions to check that the testbench is working? Or even better, is there some way to generate hex/binary code from Assembly? I have manually converted some instructions to binary and am reasonably sure the code works but am not 100% sure.

• bronzebeard

  3 36 3.9 Python

  Minimal assembler and ecosystem for bare-metal RISC-V development

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