spu32 VS esp

Compare spu32 vs esp and see what are their differences.

spu32

Small Processing Unit 32: A compact RV32I CPU written in Verilog (by maikmerten)
risc-v risc-processor Fpga Verilog system-on-chip ice40 Rv32i icestorm
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esp

Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy (by sld-columbia)
accelerators Asic Embedded Systems Fpga network-on-chip Riscv system-on-chip
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spu32 esp
1 1
60 295
- 6.8%
0.0 7.6
almost 2 years ago 10 days ago
C C
MIT License GNU General Public License v3.0 or later
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

spu32

Posts with mentions or reviews of spu32. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2021-05-10.
  • Designing instruction decoder
    2 projects | /r/FPGA | 10 May 2021
    You asked for "elegant and simple". Disregarding your request, here's how I decode RISC-V: https://github.com/maikmerten/spu32/blob/master/cpu/decoder.v

esp

Posts with mentions or reviews of esp. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-06-19.

What are some alternatives?

When comparing spu32 and esp you can also consider the following projects:

shecc - A self-hosting and educational C optimizing compiler

ara - The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

RISCV - A Pipelined RISC-V RV32I Core in Verilog [Moved to: https://github.com/georgeyhere/Toast-RV32i]

rosetta - Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ

quasiSoC - No-MMU Linux capable RISC-V SoC designed to be useful.

Vitis-HLS-Introductory-Examples

Toast-RV32i - Pipelined RISC-V RV32I Core in Verilog

Vitis-Tutorials - Vitis In-Depth Tutorials

cariboulite - CaribouLite turns any 40-pin Raspberry-Pi into a Tx/Rx 6GHz SDR

chipyard - An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

litex - Build your hardware, easily!

spu32 vs shecc esp vs ara spu32 vs RISCV esp vs rosetta spu32 vs quasiSoC esp vs Vitis-HLS-Introductory-Examples spu32 vs Toast-RV32i esp vs Vitis-Tutorials spu32 vs cariboulite esp vs chipyard spu32 vs darkriscv esp vs litex