spu32
Small Processing Unit 32: A compact RV32I CPU written in Verilog (by maikmerten)
Toast-RV32i
Pipelined RISC-V RV32I Core in Verilog (by georgeyhere)
| spu32 | Toast-RV32i | |
|---|---|---|
| 1 | 2 | |
| 60 | 34 | |
| - | - | |
| 0.0 | 0.0 | |
| almost 2 years ago | about 1 year ago | |
| C | C | |
| MIT License | - |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
spu32
Posts with mentions or reviews of spu32.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-05-10.
-
Designing instruction decoder
You asked for "elegant and simple". Disregarding your request, here's how I decode RISC-V: https://github.com/maikmerten/spu32/blob/master/cpu/decoder.v
Toast-RV32i
Posts with mentions or reviews of Toast-RV32i.
We have used some of these posts to build our list of alternatives
and similar projects.
- Intermediate FPGA project suggestions for resume
-
RV32i RISCV processor for resume - Suggestions/feedback?
Github: https://github.com/georgeyhere/Toast-RV32i
What are some alternatives?
When comparing spu32 and Toast-RV32i you can also consider the following projects:
shecc - A self-hosting and educational C optimizing compiler
riscv - RISC-V CPU Core (RV32IM)
RISCV - A Pipelined RISC-V RV32I Core in Verilog [Moved to: https://github.com/georgeyhere/Toast-RV32i]
quasiSoC - No-MMU Linux capable RISC-V SoC designed to be useful.
darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
esp - Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
openwifi - open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software
cariboulite - CaribouLite turns any 40-pin Raspberry-Pi into a Tx/Rx 6GHz SDR
NyuziProcessor - GPGPU microprocessor architecture