Toast-RV32i
darkriscv
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| Toast-RV32i | darkriscv | |
|---|---|---|
| 2 | 3 | |
| 30 | 1,582 | |
| - | 1.9% | |
| 0.0 | 6.5 | |
| over 1 year ago | 3 months ago | |
| C | Verilog | |
| - | BSD 3-clause "New" or "Revised" License |
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For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Toast-RV32i
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Tracking mentions began in Dec 2020.
darkriscv
- Are there any dual-GBE, PoE-capable SBCs?
-
Chinese Academy of Sciences releases "Xiangshan", a high performance open source RISC-V processor that runs Linux
Just found https://github.com/darklife/darkriscv whose (incomplete) core is surprisingly short. Which means you won't have to learn a lot. You can run it in simulator or on one of the listed fpga boards.
What are some alternatives?
biriscv - 32-bit Superscalar RISC-V CPU
XiangShan - Open-source high-performance RISC-V processor
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
Cores-VeeR-EH1 - VeeR EH1 core
friscv - RISCV CPU implementation in SystemVerilog
riscv - RISC-V CPU Core (RV32IM)
f4pga-examples - Example designs showing different ways to use F4PGA toolchains.
scr1 - SCR1 is a high-quality open-source RISC-V MCU core in Verilog
meta-riscv - OpenEmbedded/Yocto layer for RISC-V Architecture
open-fpga-verilog-tutorial - Learn how to design digital systems and synthesize them into an FPGA using only opensource tools
ice-chips-verilog - IceChips is a library of all common discrete logic devices in Verilog