spu32
RISCV
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spu32
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Designing instruction decoder
You asked for "elegant and simple". Disregarding your request, here's how I decode RISC-V: https://github.com/maikmerten/spu32/blob/master/cpu/decoder.v
RISCV
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Novice needs help with RISC-V toolchain
To this end, I wrote a testbench that encodes instructions and places them into a text file using SV structs. Is there any tool that can decode the output to Assembly instructions to check that the testbench is working? Or even better, is there some way to generate hex/binary code from Assembly? I have manually converted some instructions to binary and am reasonably sure the code works but am not 100% sure.
What are some alternatives?
shecc - A self-hosting and educational C optimizing compiler
bronzebeard - Minimal assembler and ecosystem for bare-metal RISC-V development
quasiSoC - No-MMU Linux capable RISC-V SoC designed to be useful.
NyuziProcessor - GPGPU microprocessor architecture
Toast-RV32i - Pipelined RISC-V RV32I Core in Verilog
openwifi - open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software
esp - Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
cariboulite - CaribouLite turns any 40-pin Raspberry-Pi into a Tx/Rx 6GHz SDR
darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
SAP1 - RTL Implementation of Malvino's SAP1. I was inspired to do this after seeing Ben Eater's Breadboard implementation