spu32
Small Processing Unit 32: A compact RV32I CPU written in Verilog (by maikmerten)
SAP1
RTL Implementation of Malvino's SAP1. I was inspired to do this after seeing Ben Eater's Breadboard implementation (by jshaker000)
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
spu32
Posts with mentions or reviews of spu32.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-05-10.
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Designing instruction decoder
You asked for "elegant and simple". Disregarding your request, here's how I decode RISC-V: https://github.com/maikmerten/spu32/blob/master/cpu/decoder.v
SAP1
Posts with mentions or reviews of SAP1.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-05-10.
-
Designing instruction decoder
Do you like this kind of a style? https://github.com/jshaker000/SAP1/blob/master/Instruction_Decoder.v
- Nand2Tetris Completed!
What are some alternatives?
When comparing spu32 and SAP1 you can also consider the following projects:
shecc - A self-hosting and educational C optimizing compiler
RISCV - A Pipelined RISC-V RV32I Core in Verilog [Moved to: https://github.com/georgeyhere/Toast-RV32i]
quasiSoC - No-MMU Linux capable RISC-V SoC designed to be useful.
Toast-RV32i - Pipelined RISC-V RV32I Core in Verilog
esp - Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
cariboulite - CaribouLite turns any 40-pin Raspberry-Pi into a Tx/Rx 6GHz SDR
darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!