ddr3-controller
A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs (by someone755)
darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night! (by darklife)
| ddr3-controller | darkriscv | |
|---|---|---|
| 3 | 3 | |
| 55 | 1,926 | |
| - | 1.8% | |
| 0.0 | 6.2 | |
| over 1 year ago | 6 days ago | |
| Verilog | Verilog | |
| - | BSD 3-clause "New" or "Revised" License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
ddr3-controller
Posts with mentions or reviews of ddr3-controller.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-05-11.
-
Best tutorial on DDR protocol
Shameless plug: Take a look at my own design. I also have apaper written about it.
-
Does anybody have a working SDRAM DDR2 Controller for Cyclone III FPGA?
If /u/UseDelicious4662 wants to port some code to their device, they could look at my DDR3 controller for Xilinx 7 Series. It's 1400 lines of code, and it's as simple as I could make it. The PHY is as good as done, even for DDR2. The logic part needs some work to be compatible with an older generation of DDR SDRAM, but overall it should be portable enough. Once that adaptation is done, they "only" need to figure out how to instantiate the Altera counterparts of OSERDES, ISERDES, and IDELAY. https://github.com/someone755/ddr3-controller
- A custom DDR3 controller for the Arty S7-50 board
darkriscv
Posts with mentions or reviews of darkriscv.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-08-20.
-
As an undergrad in my 3rd year with what feels like very little basics down, is implementing a basic RISC-V 5-stage pipelined processor on an FPGA too complex a project for an undergrad student?
This guy here has designed his 2 stage RISC-V in just one right: https://github.com/darklife/darkriscv.
- Are there any dual-GBE, PoE-capable SBCs?
-
Chinese Academy of Sciences releases "Xiangshan", a high performance open source RISC-V processor that runs Linux
Just found https://github.com/darklife/darkriscv whose (incomplete) core is surprisingly short. Which means you won't have to learn a lot. You can run it in simulator or on one of the listed fpga boards.
What are some alternatives?
When comparing ddr3-controller and darkriscv you can also consider the following projects:
control_cpu - FPGA setup with memory and Risc V CPU
biriscv - 32-bit Superscalar RISC-V CPU
simple_ddr_ctrl - A (very) simple DDR3 controller for FPGAs
XiangShan - Open-source high-performance RISC-V processor
riscv - RISC-V CPU Core (RV32IM)
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
Cores-VeeR-EH1 - VeeR EH1 core
friscv - RISCV CPU implementation in SystemVerilog
meta-riscv - OpenEmbedded/Yocto layer for RISC-V Architecture
f4pga-examples - Example designs showing different ways to use F4PGA toolchains.
open-fpga-verilog-tutorial - Learn how to design digital systems and synthesize them into an FPGA using only opensource tools
ice-chips-verilog - IceChips is a library of all common discrete logic devices in Verilog
ddr3-controller vs control_cpu
darkriscv vs biriscv
ddr3-controller vs simple_ddr_ctrl
darkriscv vs XiangShan
darkriscv vs riscv
darkriscv vs VexRiscv
darkriscv vs Cores-VeeR-EH1
darkriscv vs friscv
darkriscv vs meta-riscv
darkriscv vs f4pga-examples
darkriscv vs open-fpga-verilog-tutorial
darkriscv vs ice-chips-verilog