Best tutorial on DDR protocol

• ddr3-controller

  3 47 0.0 Verilog

  A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs

Shameless plug: Take a look at my own design. I also have apaper written about it.

• simple_ddr_ctrl

  1 2 4.8 SystemVerilog

  A (very) simple DDR3 controller for FPGAs

  

I would, of course, recommend mine. You can read it at https://github.com/CompuSAR/simple_ddr_ctrl. In particular, focus on sddr_ctrl.vs file, on those parts that work with the ddr clock. The CPU clock sections deal with control, as well as receiving the commands and returning the results. The DDR clock sections deal with the SDRAM state machine, which, I suspect, is what you're looking for.

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• control_cpu

  2 3 6.5 SystemVerilog

  FPGA setup with memory and Risc V CPU

  

I ended up using both, though you'd be excused for not seeing that from my design. This design was meant to be absolutely minimal in size, and one of the ways it does this is by assuming there is a CPU involved. So a lot of the DDR initialization is done in software (you can find it here). All register assignment and mode switching is done from there, as well as entering and leaving the write leveling mode and the whole read calibration logic.

Suggest a related project