Does anybody have a working SDRAM DDR2 Controller for Cyclone III FPGA?

• ddr3-controller

  3 55 0.0 Verilog

  A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs

If /u/UseDelicious4662 wants to port some code to their device, they could look at my DDR3 controller for Xilinx 7 Series. It's 1400 lines of code, and it's as simple as I could make it. The PHY is as good as done, even for DDR2. The logic part needs some work to be compatible with an older generation of DDR SDRAM, but overall it should be portable enough. Once that adaptation is done, they "only" need to figure out how to instantiate the Altera counterparts of OSERDES, ISERDES, and IDELAY. https://github.com/someone755/ddr3-controller

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