riscv
RISC-V CPU Core (RV32IM) (by ultraembedded)
darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night! (by darklife)
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| riscv | darkriscv | |
|---|---|---|
| 2 | 3 | |
| 1,040 | 1,882 | |
| - | 2.8% | |
| 1.8 | 6.3 | |
| over 2 years ago | 8 days ago | |
| Verilog | Verilog | |
| BSD 3-clause "New" or "Revised" License | BSD 3-clause "New" or "Revised" License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
riscv
Posts with mentions or reviews of riscv.
We have used some of these posts to build our list of alternatives
and similar projects.
-
Ultraembedded RISCV Module
I have been trying to execute some instructions to the ultraembedded riscv module https://github.com/ultraembedded/riscv
- I made my own silicon chip: Project Silicon Rider
darkriscv
Posts with mentions or reviews of darkriscv.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-08-20.
-
As an undergrad in my 3rd year with what feels like very little basics down, is implementing a basic RISC-V 5-stage pipelined processor on an FPGA too complex a project for an undergrad student?
This guy here has designed his 2 stage RISC-V in just one right: https://github.com/darklife/darkriscv.
- Are there any dual-GBE, PoE-capable SBCs?
-
Chinese Academy of Sciences releases "Xiangshan", a high performance open source RISC-V processor that runs Linux
Just found https://github.com/darklife/darkriscv whose (incomplete) core is surprisingly short. Which means you won't have to learn a lot. You can run it in simulator or on one of the listed fpga boards.
What are some alternatives?
When comparing riscv and darkriscv you can also consider the following projects:
biriscv - 32-bit Superscalar RISC-V CPU
openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
XiangShan - Open-source high-performance RISC-V processor
zipcpu - A small, light weight, RISC CPU soft core
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
Toast-RV32i - Pipelined RISC-V RV32I Core in Verilog
Cores-VeeR-EH1 - VeeR EH1 core
uhd - The USRP™ Hardware Driver Repository
friscv - RISCV CPU implementation in SystemVerilog
riscv-cores-list - RISC-V Cores, SoC platforms and SoCs
meta-riscv - OpenEmbedded/Yocto layer for RISC-V Architecture