riscv VS darkriscv

Compare riscv vs darkriscv and see what are their differences.

darkriscv

opensouce RISC-V cpu core implemented in Verilog from scratch in one night! (by darklife)
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riscv darkriscv
1 3
694 1,552
- 2.6%
0.6 6.7
over 1 year ago about 1 month ago
Verilog Verilog
BSD 3-clause "New" or "Revised" License BSD 3-clause "New" or "Revised" License
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

riscv

Posts with mentions or reviews of riscv. We have used some of these posts to build our list of alternatives and similar projects.

We haven't tracked posts mentioning riscv yet.
Tracking mentions began in Dec 2020.

darkriscv

Posts with mentions or reviews of darkriscv. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2021-08-20.

What are some alternatives?

When comparing riscv and darkriscv you can also consider the following projects:

biriscv - 32-bit Superscalar RISC-V CPU

XiangShan - Open-source high-performance RISC-V processor

VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation

openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

Cores-VeeR-EH1 - VeeR EH1 core

zipcpu - A small, light weight, RISC CPU soft core

friscv - RISCV CPU implementation in SystemVerilog

f4pga-examples - Example designs showing different ways to use F4PGA toolchains.

scr1 - SCR1 is a high-quality open-source RISC-V MCU core in Verilog

open-fpga-verilog-tutorial - Learn how to design digital systems and synthesize them into an FPGA using only opensource tools

meta-riscv - OpenEmbedded/Yocto layer for RISC-V Architecture