open-register-design-tool VS axi

Compare open-register-design-tool vs axi and see what are their differences.

open-register-design-tool

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input (by Juniper)
systemrdl jspec eda Asic Fpga registers Uvm Systemverilog register-descriptions systemrdl-compiler
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axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication (by pulp-platform)
axi Axi4 axi4-lite Systemverilog Hardware network-on-chip Asic Fpga Rtl IP
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open-register-design-tool axi
2 3
181 922
2.2% 4.9%
5.3 6.8
9 months ago about 1 month ago
Verilog SystemVerilog
Apache License 2.0 GNU General Public License v3.0 or later
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

open-register-design-tool

Posts with mentions or reviews of open-register-design-tool. We have used some of these posts to build our list of alternatives and similar projects.
  • Thoughts about SystemRDL ?
    1 project | /r/FPGA | 8 Mar 2021
    I have used this compiler (https://github.com/Juniper/open-register-design-tool/wiki/Running-Ordt) to generate a Python model to access registers (I use Python on embedded Linux to read/write registers over SPI to the device).
  • Auto Generate Header Files
    1 project | /r/FPGA | 28 Jan 2021

axi

Posts with mentions or reviews of axi. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-06-28.

What are some alternatives?

When comparing open-register-design-tool and axi you can also consider the following projects:

rggen - Code generation tool for control and status registers

chisel - Chisel: A Modern Hardware Design Language

livehd - Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

nmigen - A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen

gf180mcu-pdk - PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).

fusesoc - Package manager and build abstraction tool for FPGA/ASIC development

PeakRDL-html - Generate address space documentation HTML from compiled SystemRDL input

opentitan - OpenTitan: Open source silicon root of trust

OpenTimer - A High-performance Timing Analysis Tool for VLSI Systems

qemu - Xilinx's fork of Quick EMUlator (QEMU) with improved support and modelling for the Xilinx platforms.

biriscv - 32-bit Superscalar RISC-V CPU

Pyverilog - Python-based Hardware Design Processing Toolkit for Verilog HDL

open-register-design-tool vs rggen axi vs chisel open-register-design-tool vs livehd axi vs nmigen open-register-design-tool vs gf180mcu-pdk axi vs fusesoc open-register-design-tool vs PeakRDL-html axi vs opentitan open-register-design-tool vs OpenTimer axi vs qemu open-register-design-tool vs biriscv axi vs Pyverilog