open-register-design-tool VS biriscv

Compare open-register-design-tool vs biriscv and see what are their differences.

open-register-design-tool

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input (by Juniper)
systemrdl jspec eda Asic Fpga registers Uvm Systemverilog register-descriptions systemrdl-compiler
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biriscv

32-bit Superscalar RISC-V CPU (by ultraembedded)
risc-v Rv32i Rv32im Superscalar Cpu Fpga Verilog pipelined-processors Verilator Coremark Asic branch-prediction in-order Linux riscv-linux Xilinx artix-7
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open-register-design-tool biriscv
2 6
182 749
1.6% -
5.3 0.0
10 months ago over 2 years ago
Verilog Verilog
Apache License 2.0 Apache License 2.0
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

open-register-design-tool

Posts with mentions or reviews of open-register-design-tool. We have used some of these posts to build our list of alternatives and similar projects.
  • Thoughts about SystemRDL ?
    1 project | /r/FPGA | 8 Mar 2021
    I have used this compiler (https://github.com/Juniper/open-register-design-tool/wiki/Running-Ordt) to generate a Python model to access registers (I use Python on embedded Linux to read/write registers over SPI to the device).
  • Auto Generate Header Files
    1 project | /r/FPGA | 28 Jan 2021

biriscv

Posts with mentions or reviews of biriscv. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-06-21.

What are some alternatives?

When comparing open-register-design-tool and biriscv you can also consider the following projects:

rggen - Code generation tool for control and status registers

riscv - RISC-V CPU Core (RV32IM)

livehd - Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

gf180mcu-pdk - PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).

sdspi - SD-Card controller, using either SPI, SDIO, or eMMC interfaces

PeakRDL-html - Generate address space documentation HTML from compiled SystemRDL input

zipcpu - A small, light weight, RISC CPU soft core

OpenTimer - A High-performance Timing Analysis Tool for VLSI Systems

vgasim - A Video display simulator

axi - AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

wbicapetwo - Wishbone to ICAPE interface conversion

open-register-design-tool vs rggen biriscv vs riscv open-register-design-tool vs livehd biriscv vs darkriscv open-register-design-tool vs gf180mcu-pdk biriscv vs sdspi open-register-design-tool vs PeakRDL-html biriscv vs zipcpu open-register-design-tool vs OpenTimer biriscv vs vgasim open-register-design-tool vs axi biriscv vs wbicapetwo