Open-register-design-tool Alternatives

Similar projects and alternatives to open-register-design-tool

rggen

3 340 5.6 Ruby open-register-design-tool VS rggen

Code generation tool for control and status registers
CodeRabbit

coderabbit.ai featured

CodeRabbit: AI Code Reviews for Developers. Revolutionize your code reviews with AI. CodeRabbit offers PR summaries, code walkthroughs, 1-click suggestions, and AST-based analysis. Boost productivity and code quality across all major languages with each PR.
OpenTimer

1 569 0.0 Verilog open-register-design-tool VS OpenTimer

A High-performance Timing Analysis Tool for VLSI Systems
PeakRDL-html

1 47 2.8 JavaScript open-register-design-tool VS PeakRDL-html

Generate address space documentation HTML from compiled SystemRDL input
livehd

1 212 8.5 FIRRTL open-register-design-tool VS livehd

Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
gf180mcu-pdk

2 372 2.8 Makefile open-register-design-tool VS gf180mcu-pdk

PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).
FPGA-SDcard-Reader

1 269 3.8 Verilog open-register-design-tool VS FPGA-SDcard-Reader

An FPGA-based SD-card reader to read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器，可以从FAT16或FAT32格式的SD卡中读取文件。
biriscv

6 838 0.0 Verilog open-register-design-tool VS biriscv

32-bit Superscalar RISC-V CPU
SaaSHub

www.saashub.com featured

SaaSHub - Software Alternatives and Reviews. SaaSHub helps you find the best software and product alternatives
openlane

12 1,367 7.2 Python open-register-design-tool VS openlane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
axi

3 1,122 7.9 SystemVerilog open-register-design-tool VS axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
PeakRDL-ipxact

1 33 4.5 Python open-register-design-tool VS PeakRDL-ipxact

Import and export IP-XACT XML register models

NOTE: The number of mentions on this list indicates mentions on common posts plus user suggested alternatives. Hence, a higher number means a better open-register-design-tool alternative or higher similarity.

Suggest an alternative to open-register-design-tool

open-register-design-tool discussion

open-register-design-tool reviews and mentions

Posts with mentions or reviews of open-register-design-tool. We have used some of these posts to build our list of alternatives and similar projects.

Thoughts about SystemRDL ?
1 project | /r/FPGA | 8 Mar 2021

I have used this compiler (https://github.com/Juniper/open-register-design-tool/wiki/Running-Ordt) to generate a Python model to access registers (I use Python on embedded Linux to read/write registers over SPI to the device).
Auto Generate Header Files
1 project | /r/FPGA | 28 Jan 2021

Stats

Basic open-register-design-tool repo stats

Mentions

Stars

194

Activity

5.0

Last Commit

about 2 months ago

Juniper/open-register-design-tool is an open source project licensed under Apache License 2.0 which is an OSI approved license.

The primary programming language of open-register-design-tool is Verilog.