|5 months ago||4 days ago|
|Apache License 2.0||MIT License|
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Tracking mentions began in Dec 2020.
RgGen update (support C header file generation)
3 projects | reddit.com/r/u_taichi730 | 13 Jun 2022
RgGen is a code generation tool for configuration and status registers. RgGen can generate SV/Verilog/VHDL RTL, UVM RAL model and Markdown documents from readable register map specifications. https://github.com/rggen/rggen
4 projects | reddit.com/r/FPGA | 25 Mar 2022
I just released the latest RgGen v0.26.0! https://github.com/rggen/rggen/releases/tag/v0.26.0
What are some alternatives?
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PeakRDL-uvm - Generate UVM register model from compiled SystemRDL input
livehd - Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
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rggen-sv-rtl - Common SystemVerilog RTL modules for RgGen
openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
edalize - An abstraction library for interfacing EDA tools
PeakRDL-html - Generate address space documentation HTML from compiled SystemRDL input
biriscv - 32-bit Superscalar RISC-V CPU
axi - AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
OpenTimer - A High-performance Timing Analysis Tool for VLSI Systems