open-register-design-tool
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| open-register-design-tool | livehd | |
|---|---|---|
| 2 | 1 | |
| 181 | 197 | |
| 2.2% | 0.5% | |
| 5.3 | 9.2 | |
| 9 months ago | about 14 hours ago | |
| Verilog | Verilog | |
| Apache License 2.0 | GNU General Public License v3.0 or later |
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open-register-design-tool
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Thoughts about SystemRDL ?
I have used this compiler (https://github.com/Juniper/open-register-design-tool/wiki/Running-Ordt) to generate a Python model to access registers (I use Python on embedded Linux to read/write registers over SPI to the device).
- Auto Generate Header Files
livehd
What are some alternatives?
rggen - Code generation tool for control and status registers
hdl - HDL libraries and projects
gf180mcu-pdk - PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).
riscv - RISC-V CPU Core (RV32IM)
PeakRDL-html - Generate address space documentation HTML from compiled SystemRDL input
biriscv - 32-bit Superscalar RISC-V CPU
openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
serv - SERV - The SErial RISC-V CPU
OpenTimer - A High-performance Timing Analysis Tool for VLSI Systems
cpu11 - Revengineered ancient PDP-11 CPUs, originals and clones
axi - AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication