open-register-design-tool VS OpenTimer

Compare open-register-design-tool vs OpenTimer and see what are their differences.

open-register-design-tool

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input (by Juniper)
systemrdl jspec eda Asic Fpga registers Uvm Systemverilog register-descriptions systemrdl-compiler
Source Code
Suggest alternative
Edit details

OpenTimer

A High-performance Timing Analysis Tool for VLSI Systems (by OpenTimer)
static-timing-analysis sta vlsi vlsi-circuits vlsi-physical-design Cpp17 parallel-computing circuit-simulator Verilog electronic-design-automation computer-aided-design eda Cad circuit-simulation circuit-analysis
Source Code
Suggest alternative
Edit details
WorkOS
Our great sponsors
  • WorkOS - The modern identity platform for B2B SaaS
  • InfluxDB - Power Real-Time Data Analytics at Scale
  • SaaSHub - Software Alternatives and Reviews
Our great sponsors
open-register-design-tool OpenTimer
2 1
181 508
2.2% 1.6%
5.3 0.0
9 months ago 11 months ago
Verilog Verilog
Apache License 2.0 GNU General Public License v3.0 or later
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

open-register-design-tool

Posts with mentions or reviews of open-register-design-tool. We have used some of these posts to build our list of alternatives and similar projects.
  • Thoughts about SystemRDL ?
    1 project | /r/FPGA | 8 Mar 2021
    I have used this compiler (https://github.com/Juniper/open-register-design-tool/wiki/Running-Ordt) to generate a Python model to access registers (I use Python on embedded Linux to read/write registers over SPI to the device).
  • Auto Generate Header Files
    1 project | /r/FPGA | 28 Jan 2021

OpenTimer

Posts with mentions or reviews of OpenTimer. We have used some of these posts to build our list of alternatives and similar projects.

What are some alternatives?

When comparing open-register-design-tool and OpenTimer you can also consider the following projects:

rggen - Code generation tool for control and status registers

ice-chips-verilog - IceChips is a library of all common discrete logic devices in Verilog

gf180mcu-pdk - PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).

serv - SERV - The SErial RISC-V CPU

PeakRDL-html - Generate address space documentation HTML from compiled SystemRDL input

spydrnet - A flexible framework for analyzing and transforming FPGA netlists. Official repository.

livehd - Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

hdl - HDL libraries and projects

openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

zipcpu - A small, light weight, RISC CPU soft core

biriscv - 32-bit Superscalar RISC-V CPU

dwsim - DWSIM is a Steady-State and Dynamic Sequential Modular Chemical Process Simulator for Windows, Linux and macOS.

open-register-design-tool vs rggen OpenTimer vs ice-chips-verilog open-register-design-tool vs gf180mcu-pdk OpenTimer vs serv open-register-design-tool vs PeakRDL-html OpenTimer vs spydrnet open-register-design-tool vs livehd OpenTimer vs hdl open-register-design-tool vs openlane OpenTimer vs zipcpu open-register-design-tool vs biriscv OpenTimer vs dwsim