axi VS nmigen

Compare axi vs nmigen and see what are their differences.

axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication (by pulp-platform)
axi Axi4 axi4-lite Systemverilog Hardware network-on-chip Asic Fpga Rtl IP
Source Code
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nmigen

A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen (by m-labs)
Fpga Hdl yosys nmigen
Source Code
nmigen.org
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axi nmigen
3 3
922 643
4.9% 1.2%
6.8 1.8
about 1 month ago over 2 years ago
SystemVerilog Python
GNU General Public License v3.0 or later GNU General Public License v3.0 or later
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

axi

Posts with mentions or reviews of axi. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-06-28.

nmigen

Posts with mentions or reviews of nmigen. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2021-06-07.
  • Help a newbie
    1 project | /r/FPGA | 7 Jun 2021
    You can either decide to learn VHDL/Verilog, or use something like nmigen. I recommend learning either Verilog or VHDL anyway, so you can at least read and understand existing designs, but I personally use nmigen.
  • Do these work as JTAG programmers?
    5 projects | /r/FPGA | 7 Jun 2021
    Alternatively, you can just use Vivado to build the bitstream and then use alternative tools like https://github.com/trabucayre/openFPGALoader and http://xc3sprog.sourceforge.net/ to upload the bitstream to your FPGA. This is what I do since I use nmigen myself.
  • How to compare HDL simulation/implementation results to Matlab?
    6 projects | /r/FPGA | 1 Jun 2021

What are some alternatives?

When comparing axi and nmigen you can also consider the following projects:

chisel - Chisel: A Modern Hardware Design Language

myhdl - The MyHDL development repository

fusesoc - Package manager and build abstraction tool for FPGA/ASIC development

Pyverilog - Python-based Hardware Design Processing Toolkit for Verilog HDL

opentitan - OpenTitan: Open source silicon root of trust

pyverilator - Python wrapper for verilator model

qemu - Xilinx's fork of Quick EMUlator (QEMU) with improved support and modelling for the Xilinx platforms.

openFPGALoader - Universal utility for programming FPGA

XVC-FTDI-JTAG - Xilinx virtual cable server for generic FTDI 4232H.

Cores-VeeR-EL2 - VeeR EL2 Core

axi vs chisel nmigen vs myhdl axi vs fusesoc nmigen vs Pyverilog axi vs opentitan nmigen vs pyverilator axi vs qemu nmigen vs openFPGALoader axi vs Pyverilog nmigen vs XVC-FTDI-JTAG axi vs Cores-VeeR-EL2 nmigen vs qemu