nmigen VS pyverilator

Compare nmigen vs pyverilator and see what are their differences.

nmigen

A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen (by m-labs)
Fpga Hdl yosys nmigen
Source Code
nmigen.org
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pyverilator

Python wrapper for verilator model (by csail-csg)
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nmigen pyverilator
3 1
643 70
1.2% -
1.8 0.0
over 2 years ago 3 months ago
Python Python
GNU General Public License v3.0 or later MIT License
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nmigen

Posts with mentions or reviews of nmigen. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2021-06-07.
  • Help a newbie
    1 project | /r/FPGA | 7 Jun 2021
    You can either decide to learn VHDL/Verilog, or use something like nmigen. I recommend learning either Verilog or VHDL anyway, so you can at least read and understand existing designs, but I personally use nmigen.
  • Do these work as JTAG programmers?
    5 projects | /r/FPGA | 7 Jun 2021
    Alternatively, you can just use Vivado to build the bitstream and then use alternative tools like https://github.com/trabucayre/openFPGALoader and http://xc3sprog.sourceforge.net/ to upload the bitstream to your FPGA. This is what I do since I use nmigen myself.
  • How to compare HDL simulation/implementation results to Matlab?
    6 projects | /r/FPGA | 1 Jun 2021

pyverilator

Posts with mentions or reviews of pyverilator. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2021-06-01.
  • How to compare HDL simulation/implementation results to Matlab?
    6 projects | /r/FPGA | 1 Jun 2021
    I'd use something I could drive from Python, like https://github.com/csail-csg/pyverilator and verilator since it is fast. I'd containerize the tests and use [py.test]https://docs.pytest.org/en/6.2.x/) to run specific unit or integration tests. Ideally everything would be parameterized.

What are some alternatives?

When comparing nmigen and pyverilator you can also consider the following projects:

myhdl - The MyHDL development repository

Pyverilog - Python-based Hardware Design Processing Toolkit for Verilog HDL

qemu - Xilinx's fork of Quick EMUlator (QEMU) with improved support and modelling for the Xilinx platforms.

openFPGALoader - Universal utility for programming FPGA

axi - AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

XVC-FTDI-JTAG - Xilinx virtual cable server for generic FTDI 4232H.

xvcd - Xilinx Virtual Cable Daemon

conifer - Collect and revisit web pages.

nmigen vs myhdl pyverilator vs Pyverilog nmigen vs Pyverilog pyverilator vs qemu nmigen vs openFPGALoader pyverilator vs myhdl nmigen vs axi pyverilator vs axi nmigen vs XVC-FTDI-JTAG nmigen vs qemu nmigen vs xvcd nmigen vs conifer