nmigen
A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen (by m-labs)
qemu
Xilinx's fork of Quick EMUlator (QEMU) with improved support and modelling for the Xilinx platforms. (by Xilinx)
| nmigen | qemu | |
|---|---|---|
| 3 | 1 | |
| 643 | 225 | |
| 1.2% | 1.8% | |
| 1.8 | 4.0 | |
| over 2 years ago | 4 days ago | |
| Python | C | |
| GNU General Public License v3.0 or later | GNU General Public License v3.0 or later |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
nmigen
Posts with mentions or reviews of nmigen.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-06-07.
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Help a newbie
You can either decide to learn VHDL/Verilog, or use something like nmigen. I recommend learning either Verilog or VHDL anyway, so you can at least read and understand existing designs, but I personally use nmigen.
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Do these work as JTAG programmers?
Alternatively, you can just use Vivado to build the bitstream and then use alternative tools like https://github.com/trabucayre/openFPGALoader and http://xc3sprog.sourceforge.net/ to upload the bitstream to your FPGA. This is what I do since I use nmigen myself.
- How to compare HDL simulation/implementation results to Matlab?
qemu
Posts with mentions or reviews of qemu.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-06-01.
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How to compare HDL simulation/implementation results to Matlab?
I'd probably simulate both the accelerator and the AXI wrapper. One could instantiate a risc-v core to drive the AXI bus under simulation. gem5 or qemu see the Xilinx fork with AXI support.
What are some alternatives?
When comparing nmigen and qemu you can also consider the following projects:
myhdl - The MyHDL development repository
tpm2-tss - OSS implementation of the TCG TPM2 Software Stack (TSS2)
Pyverilog - Python-based Hardware Design Processing Toolkit for Verilog HDL
pyverilator - Python wrapper for verilator model
kvm-guest-drivers-windows - Windows paravirtualized drivers for QEMU\KVM
openFPGALoader - Universal utility for programming FPGA
axi - AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
XVC-FTDI-JTAG - Xilinx virtual cable server for generic FTDI 4232H.
keyforge-burger-inserts - Keyforge Deckbox Inserts