nmigen VS XVC-FTDI-JTAG

You can either decide to learn VHDL/Verilog, or use something like nmigen. I recommend learning either Verilog or VHDL anyway, so you can at least read and understand existing designs, but I personally use nmigen.

Alternatively, you can just use Vivado to build the bitstream and then use alternative tools like https://github.com/trabucayre/openFPGALoader and http://xc3sprog.sourceforge.net/ to upload the bitstream to your FPGA. This is what I do since I use nmigen myself.

1) Hook up programmer to the JTAG pins of your FPGA board. If you have an actual JTAG connector then there are many variations on the pinout, but the pinout can be found at https://forums.xilinx.com/t5/FPGA-Configuration/Xilinx-JTAG-Header/td-p/909793 (for example). The advantage of the Waveshare or the HS-3 cable is that you don't have to figure out the exact connector pinout, just make sure that they match. 2) Connect the programmer using USB to your laptop/desktop/workstation. 3) Run the daemon that does XVC and handles your programmer (see the repositories I linked, and also this one: https://github.com/BerkeleyLab/XVC-FTDI-JTAG). 4) In Vivado, when adding the hardware target, you should be able to add a virtual cable with an IP address and a port. There is a button called: "Add Xilinx Virtual Cable (XVC)." Vivado then just connects to the daemon that handles the actual JTAG connection.