nmigen VS axi

Compare nmigen vs axi and see what are their differences.

nmigen

A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen (by m-labs)
Fpga Hdl yosys nmigen
Source Code
nmigen.org
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axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication (by pulp-platform)
axi Axi4 axi4-lite Systemverilog Hardware network-on-chip Asic Fpga Rtl IP
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nmigen axi
3 3
643 922
1.2% 2.2%
1.8 6.8
over 2 years ago about 1 month ago
Python SystemVerilog
GNU General Public License v3.0 or later GNU General Public License v3.0 or later
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
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nmigen

Posts with mentions or reviews of nmigen. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2021-06-07.
  • Help a newbie
    1 project | /r/FPGA | 7 Jun 2021
    You can either decide to learn VHDL/Verilog, or use something like nmigen. I recommend learning either Verilog or VHDL anyway, so you can at least read and understand existing designs, but I personally use nmigen.
  • Do these work as JTAG programmers?
    5 projects | /r/FPGA | 7 Jun 2021
    Alternatively, you can just use Vivado to build the bitstream and then use alternative tools like https://github.com/trabucayre/openFPGALoader and http://xc3sprog.sourceforge.net/ to upload the bitstream to your FPGA. This is what I do since I use nmigen myself.
  • How to compare HDL simulation/implementation results to Matlab?
    6 projects | /r/FPGA | 1 Jun 2021

axi

Posts with mentions or reviews of axi. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-06-28.

What are some alternatives?

When comparing nmigen and axi you can also consider the following projects:

myhdl - The MyHDL development repository

chisel - Chisel: A Modern Hardware Design Language

Pyverilog - Python-based Hardware Design Processing Toolkit for Verilog HDL

fusesoc - Package manager and build abstraction tool for FPGA/ASIC development

pyverilator - Python wrapper for verilator model

opentitan - OpenTitan: Open source silicon root of trust

openFPGALoader - Universal utility for programming FPGA

qemu - Xilinx's fork of Quick EMUlator (QEMU) with improved support and modelling for the Xilinx platforms.

XVC-FTDI-JTAG - Xilinx virtual cable server for generic FTDI 4232H.

Cores-VeeR-EL2 - VeeR EL2 Core

nmigen vs myhdl axi vs chisel nmigen vs Pyverilog axi vs fusesoc nmigen vs pyverilator axi vs opentitan nmigen vs openFPGALoader axi vs qemu nmigen vs XVC-FTDI-JTAG axi vs Pyverilog nmigen vs qemu axi vs Cores-VeeR-EL2