axi VS fusesoc

Compare axi vs fusesoc and see what are their differences.

axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication (by pulp-platform)
axi Axi4 axi4-lite Systemverilog Hardware network-on-chip Asic Fpga Rtl IP
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fusesoc

Package manager and build abstraction tool for FPGA/ASIC development (by olofk)
Python eda Reuse package-manager Fpga Verilog Vhdl
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axi fusesoc
3 12
922 1,118
4.9% -
6.8 7.3
about 1 month ago 19 days ago
SystemVerilog Python
GNU General Public License v3.0 or later BSD 2-clause "Simplified" License
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

axi

Posts with mentions or reviews of axi. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-06-28.

fusesoc

Posts with mentions or reviews of fusesoc. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2024-03-28.

What are some alternatives?

When comparing axi and fusesoc you can also consider the following projects:

chisel - Chisel: A Modern Hardware Design Language

litex - Build your hardware, easily!

nmigen - A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen

edalize - An abstraction library for interfacing EDA tools

opentitan - OpenTitan: Open source silicon root of trust

qemu - Xilinx's fork of Quick EMUlator (QEMU) with improved support and modelling for the Xilinx platforms.

cocotb - cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

Pyverilog - Python-based Hardware Design Processing Toolkit for Verilog HDL

teroshdl-documenter-demo - This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI workflow.

Cores-VeeR-EL2 - VeeR EL2 Core

rocket-chip - Rocket Chip Generator

axi vs chisel fusesoc vs litex axi vs nmigen fusesoc vs edalize axi vs opentitan fusesoc vs opentitan axi vs qemu fusesoc vs cocotb axi vs Pyverilog fusesoc vs teroshdl-documenter-demo axi vs Cores-VeeR-EL2 fusesoc vs rocket-chip