fusesoc
Package manager and build abstraction tool for FPGA/ASIC development (by olofk)
teroshdl-documenter-demo
This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI workflow. (by TerosTechnology)
Our great sponsors
| fusesoc | teroshdl-documenter-demo | |
|---|---|---|
| 12 | 1 | |
| 1,118 | 10 | |
| - | - | |
| 7.3 | 0.0 | |
| 17 days ago | over 2 years ago | |
| Python | Python | |
| BSD 2-clause "Simplified" License | - |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
fusesoc
Posts with mentions or reviews of fusesoc.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2024-03-28.
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fusesoc VS vextproj - a user suggested alternative
2 projects | 28 Mar 2024
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Introduction to FPGAs
Check out https://github.com/olofk/fusesoc. It gives you a command line build flow that can drive Vivado (along with many other eda tools via edalize https://github.com/olofk/edalize) without having to touch the GUI (though you might want it for programming the board, though FuseSoC can do that too).
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CI/CD for FPGA builds
Check out FuseSoC: https://github.com/olofk/fusesoc it can run Vivado builds for you (as well as many other tools). It may be less work to get FuseSoC setup then work out a CLI Vivado batch flow from scratch.
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Besides misterFPGA what else can I play with on a DE10-nano?
Also, the FuseSOC and LiteX projects both support the DE10 nano, and can be used to roll your own custom SOCs with RISC-V or OpenRISC cores.
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Why isn't all verification work done in Python
Integration with the dependency and build tool I use (FuseSoc) is clumsy.
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Using Python with Vivado Projects
The "fusesoc" project may be of interest to you.
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Any recommendations for an RTL "standard library"?
FuseSoC is an RTL package manager. It will automatically download the latest versions of required components when you build. It also comes with a bunch of great options for components here:
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What should a modern IP library look like?
Have to correct this slightly: I just heard of my first HDL package manager in this thread. FuseSOC: https://github.com/olofk/fusesoc - Thanks u/gac_cag!
- Olof Kindgren on LinkedIn: We have a new world record! 6000 RISC-V cores in a single chip!
- Industry development process?
teroshdl-documenter-demo
Posts with mentions or reviews of teroshdl-documenter-demo.
We have used some of these posts to build our list of alternatives
and similar projects.
-
Open source FPGA/ASIC IDE: TerosHDL 2.0.0
I have added an example of the Documenter: https://github.com/TerosTechnology/teroshdl-documenter-demo It works with a lot of open source projects: https://terostechnology.github.io/teroshdl-documenter-demo/
What are some alternatives?
When comparing fusesoc and teroshdl-documenter-demo you can also consider the following projects:
litex - Build your hardware, easily!
cocotb - cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
edalize - An abstraction library for interfacing EDA tools
hdl_checker - Repurposing existing HDL tools to help writing better code
opentitan - OpenTitan: Open source silicon root of trust
eda-log-file-warning-suppressor - Suppresses warnings in EDA logfiles.
pymtl3 - Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
rocket-chip - Rocket Chip Generator
vcdvcd - Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.
axi - AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
fusesoc vs litex
teroshdl-documenter-demo vs cocotb
fusesoc vs edalize
teroshdl-documenter-demo vs hdl_checker
fusesoc vs opentitan
teroshdl-documenter-demo vs eda-log-file-warning-suppressor
fusesoc vs cocotb
teroshdl-documenter-demo vs pymtl3
fusesoc vs rocket-chip
teroshdl-documenter-demo vs edalize
fusesoc vs vcdvcd
fusesoc vs axi