CI/CD for FPGA builds

This page summarizes the projects mentioned and recommended in the original post on reddit.com/r/FPGA
#Vhdl #Python #eda #ghdl #Reuse

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  • fusesoc

    Package manager and build abstraction tool for FPGA/ASIC development

    Check out FuseSoC: https://github.com/olofk/fusesoc it can run Vivado builds for you (as well as many other tools). It may be less work to get FuseSoC setup then work out a CLI Vivado batch flow from scratch.

  • viv-prj-gen

    tcl scripts used to build or generate vivado projects automatically

  • Sonar

    Write Clean Python Code. Always.. Sonar helps you commit clean code every time. With over 225 unique rules to find Python bugs, code smells & vulnerabilities, Sonar finds the issues while you focus on the work.

  • ghdl

    VHDL 2008/93/87 simulator

    I'm using GHDL which doesn't have a complicated licensing scheme. ;)

  • cmd_vivado

    Simplified Command Line Interface to Xilinx's Vivado IDE

    I happened to come across this project yesterday which is a wrapper around the Vivado TCL scripts to provide a simpified CLI for use in build scripts etc.

NOTE: The number of mentions on this list indicates mentions on common posts plus user suggested alternatives. Hence, a higher number means a more popular project.

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