What should a modern IP library look like?

• fusesoc

  2 940 8.9 Python

  Package manager and build abstraction tool for FPGA/ASIC development

  Have to correct this slightly: I just heard of my first HDL package manager in this thread. FuseSOC: https://github.com/olofk/fusesoc - Thanks u/gac_cag!

• oh

  0 909 7.9 Verilog

  Verilog library for ASIC and FPGA designers (by aolofsson)

  OH!

• InfluxDB

  www.influxdata.com

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  Access the most powerful time series database as a service. Ingest, store, & analyze all types of time series data in a fully-managed, purpose-built database. Keep data forever with low-cost storage and superior data compression.

  

• VHDL_Lib

  0 183 10.0 VHDL

  Library of VHDL components that are useful in larger designs.

  VHDL_Lib

• libsv

  1 12 2.1 SystemVerilog

  An open source, parameterized SystemVerilog digital hardware IP library

  If you're interested in checking that out here's the link to the GitHub page for LibSV: https://github.com/bensampson5/libsv.

• opentitan

  5 1,749 10.0 SystemVerilog

  OpenTitan: Open source silicon root of trust

  

  https://github.com/lowRISC/opentitan - OpenTitan an Open Source root of Trust

• ibex

  5 943 8.0 SystemVerilog

  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

  

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