What should a modern IP library look like?

• fusesoc

  12 1,119 7.3 Python

  Package manager and build abstraction tool for FPGA/ASIC development

Have to correct this slightly: I just heard of my first HDL package manager in this thread. FuseSOC: https://github.com/olofk/fusesoc - Thanks u/gac_cag!

• oh

  1 1,083 4.0 Verilog

  Verilog library for ASIC and FPGA designers (by aolofsson)

OH!

• InfluxDB

  www.influxdata.com featured

  Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.

  

• VHDL_Lib

  1 218 2.5 VHDL

  Library of VHDL components that are useful in larger designs.

VHDL_Lib

• libsv

  2 19 3.6 SystemVerilog

  An open source, parameterized SystemVerilog digital hardware IP library

If you're interested in checking that out here's the link to the GitHub page for LibSV: https://github.com/bensampson5/libsv.

• opentitan

  14 2,365 10.0 SystemVerilog

  OpenTitan: Open source silicon root of trust

  

https://github.com/lowRISC/opentitan - OpenTitan an Open Source root of Trust

• ibex

  21 1,257 8.3 SystemVerilog

  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

  

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