Fusesoc Alternatives

Similar projects and alternatives to fusesoc

• neorv32

  77 1,415 9.9 C fusesoc VS neorv32

  :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

• litex

  29 2,683 9.7 C fusesoc VS litex

  Build your hardware, easily!

• InfluxDB

  www.influxdata.com sponsored

  Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.

  

• ghdl

  26 2,206 9.8 VHDL fusesoc VS ghdl

  VHDL 2008/93/87 simulator

  

• chisel

  25 3,708 9.7 Scala fusesoc VS chisel

  Chisel: A Modern Hardware Design Language (by chipsalliance)

  

• satcat5

  25 387 3.8 VHDL fusesoc VS satcat5

  SatCat5 is a mixed-media Ethernet switch that lets a variety of devices communicate on the same network.

  

• opentitan

  14 2,349 10.0 SystemVerilog fusesoc VS opentitan

  OpenTitan: Open source silicon root of trust

  

• ibex

  20 1,237 8.5 SystemVerilog fusesoc VS ibex

  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

  

• WorkOS

  workos.com sponsored

  The modern identity platform for B2B SaaS. The APIs are flexible and easy-to-use, supporting authentication, user identity, and complex enterprise features like SSO and SCIM provisioning.

  

• serv

  19 1,244 7.7 Verilog fusesoc VS serv

  SERV - The SErial RISC-V CPU

• de10-nano

  14 169 3.3 Shell fusesoc VS de10-nano

  Absolute beginner's guide to the de10-nano

• edalize

  4 590 7.3 Python fusesoc VS edalize

  An abstraction library for interfacing EDA tools

• viv-prj-gen

  8 21 1.9 CMake fusesoc VS viv-prj-gen

  tcl scripts used to build or generate vivado projects automatically

• hdl

  5 1,374 9.0 Verilog fusesoc VS hdl

  HDL libraries and projects

  

• cocotb

  28 1,599 9.7 Python fusesoc VS cocotb

  cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

  

• axi

  3 922 6.8 SystemVerilog fusesoc VS axi

  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

  

• teroshdl-documenter-demo

  1 10 0.0 Python fusesoc VS teroshdl-documenter-demo

  This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI workflow.

  

• rocket-chip

  12 3,002 8.3 Scala fusesoc VS rocket-chip

  Rocket Chip Generator

  

• basejump_stl

  4 445 6.2 SystemVerilog fusesoc VS basejump_stl

  BaseJump STL: A Standard Template Library for SystemVerilog

  

• vcdvcd

  1 49 5.9 Python fusesoc VS vcdvcd

  Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.

• Free-Range-VHDL-book

  3 236 6.0 TeX fusesoc VS Free-Range-VHDL-book

  Latex source files of the open-source book FREE RANGE VHDL

• blinky

  2 151 5.7 Tcl fusesoc VS blinky

  Example LED blinking project for your FPGA dev board of choice (by fusesoc)

  

• SaaSHub

  www.saashub.com sponsored

  SaaSHub - Software Alternatives and Reviews. SaaSHub helps you find the best software and product alternatives