teroshdl-documenter-demo
This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI workflow. (by TerosTechnology)
hdl_checker
Repurposing existing HDL tools to help writing better code (by suoto)
teroshdl-documenter-demo | hdl_checker | |
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1 | 4 | |
10 | 184 | |
- | - | |
0.0 | 0.0 | |
over 2 years ago | 5 months ago | |
Python | Python | |
- | GNU General Public License v3.0 only |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
teroshdl-documenter-demo
Posts with mentions or reviews of teroshdl-documenter-demo.
We have used some of these posts to build our list of alternatives
and similar projects.
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Open source FPGA/ASIC IDE: TerosHDL 2.0.0
I have added an example of the Documenter: https://github.com/TerosTechnology/teroshdl-documenter-demo It works with a lot of open source projects: https://terostechnology.github.io/teroshdl-documenter-demo/
hdl_checker
Posts with mentions or reviews of hdl_checker.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-02-23.
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Any better options than Sigasi?
I've written a LSP that uses modelsim, ghdl or Vivado to do error checking: https://github.com/suoto/hdl_checker
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What Editor is Everyone Using for FPGA design? (2021)
NeoVim + CoC + hdl_checker
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VHDL native lsp
As others mentioned, rust_hdl and ghdl ls are worth checking out. If your project has both VHDL and Verilog/SystemVerilog, might be worth checking https://github.com/suoto/hdl_checker (disclaimer, I'm the author). It's got less LS features than the other two but if you use it with modelsim it'll provide mixed language syntax check.
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IDE / Editor of choice
Specifically for HDL-files a lot of progress has been made in the last couple of years on lsp-mode and external LSP servers for code analysis of both VHDL and SystemVerilog. For SV I use the https://github.com/suoto/hdl_checker server that passes the code you are working on live to the Linting engine in Questa/ModelSim and marks the warning lines in the editor. It's nice to get immediate feedback on missing semicolons etc. although it still has a hard time handling large projects.
What are some alternatives?
When comparing teroshdl-documenter-demo and hdl_checker you can also consider the following projects:
cocotb - cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
completor.vim - Async completion framework made ease.
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development
rust_hdl
eda-log-file-warning-suppressor - Suppresses warnings in EDA logfiles.
veridian - A SystemVerilog Language Server
pymtl3 - Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
edalize - An abstraction library for interfacing EDA tools
vscode-terosHDL - VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
cocotb-bus - Pre-packaged testbenching tools and reusable bus interfaces for cocotb
teroshdl-documenter-demo vs cocotb
hdl_checker vs completor.vim
teroshdl-documenter-demo vs fusesoc
hdl_checker vs rust_hdl
teroshdl-documenter-demo vs eda-log-file-warning-suppressor
hdl_checker vs veridian
teroshdl-documenter-demo vs pymtl3
hdl_checker vs cocotb
teroshdl-documenter-demo vs edalize
hdl_checker vs vscode-terosHDL
hdl_checker vs edalize
hdl_checker vs cocotb-bus