hdl_checker
veridian
hdl_checker | veridian | |
---|---|---|
4 | 3 | |
183 | 106 | |
- | - | |
0.0 | 4.8 | |
4 months ago | about 2 months ago | |
Python | Rust | |
GNU General Public License v3.0 only | MIT License |
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hdl_checker
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Any better options than Sigasi?
I've written a LSP that uses modelsim, ghdl or Vivado to do error checking: https://github.com/suoto/hdl_checker
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What Editor is Everyone Using for FPGA design? (2021)
NeoVim + CoC + hdl_checker
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VHDL native lsp
As others mentioned, rust_hdl and ghdl ls are worth checking out. If your project has both VHDL and Verilog/SystemVerilog, might be worth checking https://github.com/suoto/hdl_checker (disclaimer, I'm the author). It's got less LS features than the other two but if you use it with modelsim it'll provide mixed language syntax check.
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IDE / Editor of choice
Specifically for HDL-files a lot of progress has been made in the last couple of years on lsp-mode and external LSP servers for code analysis of both VHDL and SystemVerilog. For SV I use the https://github.com/suoto/hdl_checker server that passes the code you are working on live to the Linting engine in Questa/ModelSim and marks the warning lines in the editor. It's nice to get immediate feedback on missing semicolons etc. although it still has a hard time handling large projects.
veridian
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How to configure vim like an IDE
SystemVerilog
- Tools like Scitools Understand but support Verilog
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Are you using tree-sitter via nvim-treesitter plugin?
Neovim's native LSP support with Slang and/or Verible + https://github.com/vivekmalneedi/veridian
What are some alternatives?
completor.vim - Async completion framework made ease.
verilog_systemverilog.vim - Verilog/SystemVerilog Syntax and Omni-completion
rust_hdl
verible - Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
cocotb - cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
svls - SystemVerilog language server
teroshdl-documenter-demo - This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI workflow.
svlint - SystemVerilog linter
vscode-terosHDL - VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
iverilog - Icarus Verilog
edalize - An abstraction library for interfacing EDA tools
slang - SystemVerilog compiler and language services