hdl_checker
vscode-terosHDL
hdl_checker | vscode-terosHDL | |
---|---|---|
4 | 3 | |
183 | 495 | |
- | 3.2% | |
0.0 | 9.2 | |
4 months ago | 7 days ago | |
Python | JavaScript | |
GNU General Public License v3.0 only | GNU General Public License v3.0 only |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
hdl_checker
-
Any better options than Sigasi?
I've written a LSP that uses modelsim, ghdl or Vivado to do error checking: https://github.com/suoto/hdl_checker
-
What Editor is Everyone Using for FPGA design? (2021)
NeoVim + CoC + hdl_checker
-
VHDL native lsp
As others mentioned, rust_hdl and ghdl ls are worth checking out. If your project has both VHDL and Verilog/SystemVerilog, might be worth checking https://github.com/suoto/hdl_checker (disclaimer, I'm the author). It's got less LS features than the other two but if you use it with modelsim it'll provide mixed language syntax check.
-
IDE / Editor of choice
Specifically for HDL-files a lot of progress has been made in the last couple of years on lsp-mode and external LSP servers for code analysis of both VHDL and SystemVerilog. For SV I use the https://github.com/suoto/hdl_checker server that passes the code you are working on live to the Linting engine in Questa/ModelSim and marks the warning lines in the editor. It's nice to get immediate feedback on missing semicolons etc. although it still has a hard time handling large projects.
vscode-terosHDL
-
Sigasi's price
You can try TerosHDL: https://terostechnology.github.io/terosHDLdoc/
- (System)Verilog Linting in VSCode?
-
sublime System Verilog vs TerosHDL VS Code vs Synopsys Euclide
Please, open an issue in: https://github.com/TerosTechnology/vscode-terosHDL
What are some alternatives?
completor.vim - Async completion framework made ease.
rggen - Code generation tool for control and status registers
rust_hdl
hdlConvertor - Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
veridian - A SystemVerilog Language Server
verilog_template - A template for starting a Verilog project with FuseSoC integration, Icarus simulation, Verilator linting, Yosys usage report, and VS Code syntax highlighting.
cocotb - cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
oss-cad-suite-build - Multi-platform nightly builds of open source digital design and verification tools
teroshdl-documenter-demo - This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI workflow.
edalize - An abstraction library for interfacing EDA tools
clash-ghc - Haskell to VHDL/Verilog/SystemVerilog compiler