IDE / Editor of choice

This page summarizes the projects mentioned and recommended in the original post on /r/FPGA
Vhdl modelsim Xilinx Verilog Systemverilog

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  • hdl_checker

    Repurposing existing HDL tools to help writing better code

    • Specifically for HDL-files a lot of progress has been made in the last couple of years on lsp-mode and external LSP servers for code analysis of both VHDL and SystemVerilog. For SV I use the https://github.com/suoto/hdl_checker server that passes the code you are working on live to the Linting engine in Questa/ModelSim and marks the warning lines in the editor. It's nice to get immediate feedback on missing semicolons etc. although it still has a hard time handling large projects.

  • InfluxDB

    Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.

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NOTE: The number of mentions on this list indicates mentions on common posts plus user suggested alternatives. Hence, a higher number means a more popular project.

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