Hdl_checker Alternatives

Similar projects and alternatives to hdl_checker

  1. rust_hdl

    A fast VHDL language server and analysis library written in Rust

  2. SaaSHub

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  3. completor.vim

    Async completion framework made ease.

  4. vscode-terosHDL

    VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

  5. edalize

    An abstraction library for interfacing EDA tools

  6. veridian

    A SystemVerilog Language Server

  7. teroshdl-documenter-demo

    Discontinued This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI workflow.

  8. cocotb-bus

    Pre-packaged testbenching tools and reusable bus interfaces for cocotb

  9. vcdvcd

    Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.

  10. anakin-language-server

    Yet another Jedi Python language server

NOTE: The number of mentions on this list indicates mentions on common posts plus user suggested alternatives. Hence, a higher number means a better hdl_checker alternative or higher similarity.

hdl_checker discussion

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hdl_checker reviews and mentions

Posts with mentions or reviews of hdl_checker. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-02-23.
  • Any better options than Sigasi?
    2 projects | /r/FPGA | 23 Feb 2022
    I've written a LSP that uses modelsim, ghdl or Vivado to do error checking: https://github.com/suoto/hdl_checker
  • What Editor is Everyone Using for FPGA design? (2021)
    2 projects | /r/FPGA | 28 Jun 2021
    NeoVim + CoC + hdl_checker
  • VHDL native lsp
    1 project | /r/neovim | 24 Jun 2021
    As others mentioned, rust_hdl and ghdl ls are worth checking out. If your project has both VHDL and Verilog/SystemVerilog, might be worth checking https://github.com/suoto/hdl_checker (disclaimer, I'm the author). It's got less LS features than the other two but if you use it with modelsim it'll provide mixed language syntax check.
  • IDE / Editor of choice
    1 project | /r/FPGA | 19 Mar 2021
    Specifically for HDL-files a lot of progress has been made in the last couple of years on lsp-mode and external LSP servers for code analysis of both VHDL and SystemVerilog. For SV I use the https://github.com/suoto/hdl_checker server that passes the code you are working on live to the Linting engine in Questa/ModelSim and marks the warning lines in the editor. It's nice to get immediate feedback on missing semicolons etc. although it still has a hard time handling large projects.
  • A note from our sponsor - SaaSHub
    www.saashub.com | 19 Aug 2026
    SaaSHub helps you find the best software and product alternatives Learn more →

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Basic hdl_checker repo stats
4
226
0.0
about 2 months ago

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