(System)Verilog Linting in VSCode?

• vscode-terosHDL

  3 574 9.1 VHDL

  VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

  

• SaaSHub

  www.saashub.com featured

  SaaSHub - Software Alternatives and Reviews. SaaSHub helps you find the best software and product alternatives

  

• verilog_template

  1 1 2.6 Makefile

  A template for starting a Verilog project with FuseSoC integration, Icarus simulation, Verilator linting, Yosys usage report, and VS Code syntax highlighting.

  I have success with iverilog linting! Here is an example project with the settings configured: https://github.com/E4tHam/verilog_template

• oss-cad-suite-build

  14 876 8.3 Shell

  Multi-platform nightly builds of open source digital design and verification tools

  

  You’ll need to install the latest iverilog version. The easiest way to do that is to install https://github.com/YosysHQ/oss-cad-suite-build

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