(System)Verilog Linting in VSCode?

This page summarizes the projects mentioned and recommended in the original post on /r/FPGA
Verilog Vhdl Systemverilog Fpga

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SaaSHub helps you find the best software and product alternatives
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  • vscode-terosHDL

    VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

  • verilog_template

    A template for starting a Verilog project with FuseSoC integration, Icarus simulation, Verilator linting, Yosys usage report, and VS Code syntax highlighting.

    • I have success with iverilog linting! Here is an example project with the settings configured: https://github.com/E4tHam/verilog_template

  • InfluxDB

    Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.

    InfluxDB logo

  • oss-cad-suite-build

    Multi-platform nightly builds of open source digital design and verification tools

    • You’ll need to install the latest iverilog version. The easiest way to do that is to install https://github.com/YosysHQ/oss-cad-suite-build

NOTE: The number of mentions on this list indicates mentions on common posts plus user suggested alternatives. Hence, a higher number means a more popular project.

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