Suggest an alternative to

vscode-terosHDL

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

A URL to the alternative repo (e.g. GitHub, GitLab)

Here you can share your experience with the project you are suggesting or its comparison with vscode-terosHDL. Optional.

A valid email to send you a verification link when necessary or log in.