hdl_checker VS teroshdl-documenter-demo

Compare hdl_checker vs teroshdl-documenter-demo and see what are their differences.

hdl_checker

Repurposing existing HDL tools to help writing better code (by suoto)
Vhdl modelsim Xilinx Verilog Systemverilog Python Hdl xilinx-vivado syntax-checker lsp-server vivado-simulator ghdl Vim hdl-checker language-server coc-nvim questasim mentor-msim vim-ale emacs-lsp
Source Code
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teroshdl-documenter-demo

This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI workflow. (by TerosTechnology)
Vhdl Verilog Systemverilog
Source Code
terostechnology.github.io
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hdl_checker teroshdl-documenter-demo
4 1
183 10
- -
0.0 0.0
4 months ago over 2 years ago
Python Python
GNU General Public License v3.0 only -
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hdl_checker

Posts with mentions or reviews of hdl_checker. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-02-23.
  • Any better options than Sigasi?
    2 projects | /r/FPGA | 23 Feb 2022
    I've written a LSP that uses modelsim, ghdl or Vivado to do error checking: https://github.com/suoto/hdl_checker
  • What Editor is Everyone Using for FPGA design? (2021)
    2 projects | /r/FPGA | 28 Jun 2021
    NeoVim + CoC + hdl_checker
  • VHDL native lsp
    1 project | /r/neovim | 24 Jun 2021
    As others mentioned, rust_hdl and ghdl ls are worth checking out. If your project has both VHDL and Verilog/SystemVerilog, might be worth checking https://github.com/suoto/hdl_checker (disclaimer, I'm the author). It's got less LS features than the other two but if you use it with modelsim it'll provide mixed language syntax check.
  • IDE / Editor of choice
    1 project | /r/FPGA | 19 Mar 2021
    Specifically for HDL-files a lot of progress has been made in the last couple of years on lsp-mode and external LSP servers for code analysis of both VHDL and SystemVerilog. For SV I use the https://github.com/suoto/hdl_checker server that passes the code you are working on live to the Linting engine in Questa/ModelSim and marks the warning lines in the editor. It's nice to get immediate feedback on missing semicolons etc. although it still has a hard time handling large projects.

teroshdl-documenter-demo

Posts with mentions or reviews of teroshdl-documenter-demo. We have used some of these posts to build our list of alternatives and similar projects.
  • Open source FPGA/ASIC IDE: TerosHDL 2.0.0
    1 project | /r/FPGA | 29 Sep 2021
    I have added an example of the Documenter: https://github.com/TerosTechnology/teroshdl-documenter-demo It works with a lot of open source projects: https://terostechnology.github.io/teroshdl-documenter-demo/

What are some alternatives?

When comparing hdl_checker and teroshdl-documenter-demo you can also consider the following projects:

completor.vim - Async completion framework made ease.

cocotb - cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

rust_hdl

fusesoc - Package manager and build abstraction tool for FPGA/ASIC development

veridian - A SystemVerilog Language Server

eda-log-file-warning-suppressor - Suppresses warnings in EDA logfiles.

pymtl3 - Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework

vscode-terosHDL - VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

edalize - An abstraction library for interfacing EDA tools

cocotb-bus - Pre-packaged testbenching tools and reusable bus interfaces for cocotb

hdl_checker vs completor.vim teroshdl-documenter-demo vs cocotb hdl_checker vs rust_hdl teroshdl-documenter-demo vs fusesoc hdl_checker vs veridian teroshdl-documenter-demo vs eda-log-file-warning-suppressor hdl_checker vs cocotb teroshdl-documenter-demo vs pymtl3 hdl_checker vs vscode-terosHDL teroshdl-documenter-demo vs edalize hdl_checker vs edalize hdl_checker vs cocotb-bus