Tools like Scitools Understand but support Verilog

This page summarizes the projects mentioned and recommended in the original post on /r/FPGA

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  • verible

    Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

  • https://github.com/chipsalliance/verible (may not do actual syntax checking)

  • iverilog

    Icarus Verilog

  • https://github.com/steveicarus/iverilog (can definitely do syntax checking, but is missing some functionality for newer Verilog standards)

  • WorkOS

    The modern identity platform for B2B SaaS. The APIs are flexible and easy-to-use, supporting authentication, user identity, and complex enterprise features like SSO and SCIM provisioning.

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  • slang

    SystemVerilog compiler and language services (by MikePopoloski)

  • veridian

    A SystemVerilog Language Server

NOTE: The number of mentions on this list indicates mentions on common posts plus user suggested alternatives. Hence, a higher number means a more popular project.

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