veridian
slang
veridian | slang | |
---|---|---|
3 | 4 | |
106 | 536 | |
- | - | |
4.8 | 9.7 | |
about 2 months ago | 1 day ago | |
Rust | C++ | |
MIT License | MIT License |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
veridian
-
How to configure vim like an IDE
SystemVerilog
- Tools like Scitools Understand but support Verilog
-
Are you using tree-sitter via nvim-treesitter plugin?
Neovim's native LSP support with Slang and/or Verible + https://github.com/vivekmalneedi/veridian
slang
- Is anyone aware of a commercial parser that converts modern system verilog, UVM, etc to JSON or YAML?
- Tools like Scitools Understand but support Verilog
- What cli tool can give me a list of input/ouput pins of my verilog modules?
-
AMD Patent Reveals Hybrid CPU-FPGA Design That Could Be Enabled by Xilinx Tech
Going to plug my work on this here: https://github.com/MikePopoloski/slang
At some point I'd like to see it integrated as the frontend to tools like Yosys to get best-in-class SystemVerilog support in open tools.
What are some alternatives?
verilog_systemverilog.vim - Verilog/SystemVerilog Syntax and Omni-completion
verible - Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
hdl_checker - Repurposing existing HDL tools to help writing better code
Surelog - SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
iverilog - Icarus Verilog
svls - SystemVerilog language server
json - A C++11 library for parsing and serializing JSON to and from a DOM container in memory.
svlint - SystemVerilog linter
Surelog - SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
nvim-treesitter - Nvim Treesitter configurations and abstraction layer