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Top 12 C++ Verilog Projects
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InfluxDB
Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.
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Surelog
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX (by chipsalliance)
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hdlConvertor
Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
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WorkOS
The modern identity platform for B2B SaaS. The APIs are flexible and easy-to-use, supporting authentication, user identity, and complex enterprise features like SSO and SCIM provisioning.
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metron
A C++ to Verilog translation tool with some basic guarantees that your code will work. (by aappleby)
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karuta
Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for FPGA development.
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You may want to check out Verilator:
https://verilator.org/
He wrote a game engine, it renders transparent items using the painter's algorithm, which requires the items to be sorted in Z. He has a routine that iterates over all items to render them, and bubble-sorts the items in-place while iterating over the items (all in the same thread). The "compare and swap" in this case is the innermost functionality of bubblesort.
I assume the author is https://github.com/aappleby but I don't see any obvious candidate for this code. Maybe this? https://github.com/aappleby/metroboy but I can't see why a gate-level emulator woudl need to render transparent items using painter's algorithm.
Project mention: WebSDR – internet connected Software-Defined Radios | news.ycombinator.com | 2023-10-26If you want to have something similar for use at home, you could take a look at http://kiwisdr.com.
I have one, but you need to hunt down EMI sources, before you can properly use it.
Project mention: Semi-automatic VLSI reverse engineering of digital logic in chips | news.ycombinator.com | 2024-02-02
Hi everyone, If you need to build C++ (or Python) application loading gate level verilog, similar to the one at the input of FPGA PnR tools, https://github.com/xtofalex/naja-verilog is available. This parser has been designed to allow the construction on the fly of any netlist data structure. One note: if you need also a C++ netlist data structure (with Python bindings) to build netlist analysis or editing tools on top, Naja SNL: https://github.com/xtofalex/naja is also ready for use. Hope this is useful. If it is or if you face any issue, please reach to me. Feedback welcome.
NOTE:
The open source projects on this list are ordered by number of github stars.
The number of mentions indicates repo mentiontions in the last 12 Months or
since we started tracking (Dec 2020).
C++ Verilog related posts
- Semi-automatic VLSI reverse engineering of digital logic in chips
- When would you ever want bubblesort?
- What's new for RISC-V in LLVM 17
- Naja-Verilog: stand-alone structural (gate-level) parser
- 500 Lines or Less – Writing a useful program in fewer than 500 line code – AOSA
- Documentation for cycle accurate Game Boy CPU
- Show HN: Naja-Verilog – Structural Verilog Parser
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A note from our sponsor - WorkOS
workos.com | 24 Apr 2024
Index
What are some of the best open-source Verilog projects in C++? This list will help you:
| Project | Stars | |
|---|---|---|
| 1 | verilator | 2,083 |
| 2 | metroboy | 1,089 |
| 3 | slang | 533 |
| 4 | Beagle_SDR_GPS | 453 |
| 5 | Surelog | 329 |
| 6 | hdlConvertor | 264 |
| 7 | Degate | 229 |
| 8 | dblclockfft | 204 |
| 9 | metron | 151 |
| 10 | karuta | 97 |
| 11 | cordic | 77 |
| 12 | naja-verilog | 21 |
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