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Top 11 C++ Verilog Projects
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This looks really cool!
A nitpick: the Verilog simulation seems to be handled by the open-source Verilator projct, which is packaged as a binary WASM blob without any acknowledgement or source code. I don't think that's compliant with either of the licenses under which Verilator is distributed (LGPL-3.0 or Artistic License).
https://github.com/verilator/verilator
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Project mention: Ask HN: What Are You Working On? (October 2024) | news.ycombinator.com | 2024-10-27
As a software developer who later got into hardware design, I've always been pretty disappointed with the quality of HDL tools. You get a bit spoiled by the quality of compilers like gcc and clang, and then you run into ridiculously expensive closed-source SystemVerilog compilers that fall apart on valid and obvious code, can't be run in a build farm, and which report cryptic messages for errors. So I've been working on my own open source SystemVerilog compiler / frontend for a while now, and it's nearing 100% completion in terms of language support.
https://github.com/MikePopoloski/slang
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Surelog
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX (by chipsalliance)
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hdlConvertor
Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
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metron
A C++ to Verilog translation tool with some basic guarantees that your code will work. (by aappleby)
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karuta
Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for FPGA development.
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NOTE:
The open source projects on this list are ordered by number of github stars.
The number of mentions indicates repo mentiontions in the last 12 Months or
since we started tracking (Dec 2020).
C++ Verilog discussion
C++ Verilog related posts
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Tiny Tapeout VGA Playground
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Yosys and slang: A match made in heaven
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Show HN: Naja_edit – an EDA tool designed for optimizing gate-level netlists
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Verilator: Open-Source SystemVerilog simulator and lint system
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Semi-automatic VLSI reverse engineering of digital logic in chips
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When would you ever want bubblesort?
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What's new for RISC-V in LLVM 17
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Index
What are some of the best open-source Verilog projects in C++? This list will help you:
| # | Project | Stars |
|---|---|---|
| 1 | verilator | 2,763 |
| 2 | metroboy | 1,133 |
| 3 | slang | 693 |
| 4 | Surelog | 382 |
| 5 | hdlConvertor | 288 |
| 6 | Degate | 256 |
| 7 | dblclockfft | 231 |
| 8 | metron | 166 |
| 9 | karuta | 101 |
| 10 | cordic | 97 |
| 11 | naja-verilog | 34 |
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