slang
verible
| slang | verible | |
|---|---|---|
| 4 | 6 | |
| 535 | 1,197 | |
| - | 1.8% | |
| 9.7 | 9.3 | |
| 8 days ago | 12 days ago | |
| C++ | C++ | |
| MIT License | GNU General Public License v3.0 or later |
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slang
- Is anyone aware of a commercial parser that converts modern system verilog, UVM, etc to JSON or YAML?
- Tools like Scitools Understand but support Verilog
- What cli tool can give me a list of input/ouput pins of my verilog modules?
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AMD Patent Reveals Hybrid CPU-FPGA Design That Could Be Enabled by Xilinx Tech
Going to plug my work on this here: https://github.com/MikePopoloski/slang
At some point I'd like to see it integrated as the frontend to tools like Yosys to get best-in-class SystemVerilog support in open tools.
verible
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How to instance module with auto-completion for verilog in neovim?
I want to write Verilog/SystemVerilog with neovim(I use Lazyvim,nvim-lspconfig,mason.nvim, mason-lspconfig.nvim and nvim-cmp) . Now I use Verible to format and lint. But it seems that it cannot complete the signals when I want to instance a module and type a "." . So is there a better way to interconnect modules?
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Verilog LRM syntax rules
BTW, I'd recommend checking out verible if you're looking for a flex/bison verilog parser.
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Reliable Verilog dependency analysis
You'll have to roll up your sleeves a bit, but Verible might be worth a look for a functional SystemVerilog parser that you could build off of. It's the only thing I'm aware of built for this class of tools (e.g. yosys is only synthesizable verilog) that's available and likely to cover a good amount of the spec.
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svls VS verible - a user suggested alternative
2 projects | 3 Nov 2021
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Tools like Scitools Understand but support Verilog
https://github.com/chipsalliance/verible (may not do actual syntax checking)
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Forking rustfmt for another language
You might be interested in this though.
What are some alternatives?
Surelog - SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
svls - SystemVerilog language server
iverilog - Icarus Verilog
json - A C++11 library for parsing and serializing JSON to and from a DOM container in memory.
veridian - A SystemVerilog Language Server
Surelog - SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
tree-sitter-html - HTML grammar for Tree-sitter
f4pga-arch-defs - FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.