verible
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server (by chipsalliance)
veridian
A SystemVerilog Language Server (by vivekmalneedi)
| verible | veridian | |
|---|---|---|
| 6 | 3 | |
| 1,189 | 104 | |
| 1.2% | - | |
| 9.3 | 4.8 | |
| 8 days ago | about 2 months ago | |
| C++ | Rust | |
| GNU General Public License v3.0 or later | MIT License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
verible
Posts with mentions or reviews of verible.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-02-05.
-
How to instance module with auto-completion for verilog in neovim?
I want to write Verilog/SystemVerilog with neovim(I use Lazyvim,nvim-lspconfig,mason.nvim, mason-lspconfig.nvim and nvim-cmp) . Now I use Verible to format and lint. But it seems that it cannot complete the signals when I want to instance a module and type a "." . So is there a better way to interconnect modules?
-
Verilog LRM syntax rules
BTW, I'd recommend checking out verible if you're looking for a flex/bison verilog parser.
-
Reliable Verilog dependency analysis
You'll have to roll up your sleeves a bit, but Verible might be worth a look for a functional SystemVerilog parser that you could build off of. It's the only thing I'm aware of built for this class of tools (e.g. yosys is only synthesizable verilog) that's available and likely to cover a good amount of the spec.
-
svls VS verible - a user suggested alternative
2 projects | 3 Nov 2021
-
Tools like Scitools Understand but support Verilog
https://github.com/chipsalliance/verible (may not do actual syntax checking)
-
Forking rustfmt for another language
You might be interested in this though.
veridian
Posts with mentions or reviews of veridian.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-06-27.
-
How to configure vim like an IDE
SystemVerilog
- Tools like Scitools Understand but support Verilog
-
Are you using tree-sitter via nvim-treesitter plugin?
Neovim's native LSP support with Slang and/or Verible + https://github.com/vivekmalneedi/veridian
What are some alternatives?
When comparing verible and veridian you can also consider the following projects:
slang - SystemVerilog compiler and language services
verilog_systemverilog.vim - Verilog/SystemVerilog Syntax and Omni-completion
svls - SystemVerilog language server
hdl_checker - Repurposing existing HDL tools to help writing better code
Surelog - SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
Surelog - SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
svlint - SystemVerilog linter
tree-sitter-html - HTML grammar for Tree-sitter
iverilog - Icarus Verilog