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Verible Alternatives
Similar projects and alternatives to verible
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f4pga-arch-defs
FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
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WorkOS
The modern identity platform for B2B SaaS. The APIs are flexible and easy-to-use, supporting authentication, user identity, and complex enterprise features like SSO and SCIM provisioning.
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Surelog
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
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Surelog
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX (by chipsalliance)
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InfluxDB
Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.
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NOTE:
The number of mentions on this list indicates mentions on common posts plus user suggested alternatives.
Hence, a higher number means a better verible alternative or higher similarity.
verible reviews and mentions
Posts with mentions or reviews of verible.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-02-05.
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How to instance module with auto-completion for verilog in neovim?
I want to write Verilog/SystemVerilog with neovim(I use Lazyvim,nvim-lspconfig,mason.nvim, mason-lspconfig.nvim and nvim-cmp) . Now I use Verible to format and lint. But it seems that it cannot complete the signals when I want to instance a module and type a "." . So is there a better way to interconnect modules?
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Verilog LRM syntax rules
BTW, I'd recommend checking out verible if you're looking for a flex/bison verilog parser.
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Reliable Verilog dependency analysis
You'll have to roll up your sleeves a bit, but Verible might be worth a look for a functional SystemVerilog parser that you could build off of. It's the only thing I'm aware of built for this class of tools (e.g. yosys is only synthesizable verilog) that's available and likely to cover a good amount of the spec.
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svls VS verible - a user suggested alternative
2 projects | 3 Nov 2021
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Tools like Scitools Understand but support Verilog
https://github.com/chipsalliance/verible (may not do actual syntax checking)
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Forking rustfmt for another language
You might be interested in this though.
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A note from our sponsor - InfluxDB
www.influxdata.com | 18 Apr 2024
Stats
Basic verible repo stats
6
1,185
9.3
3 days ago
chipsalliance/verible is an open source project licensed under GNU General Public License v3.0 or later which is an OSI approved license.
The primary programming language of verible is C++.
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