SaaSHub helps you find the best software and product alternatives Learn more →
Verible Alternatives
Similar projects and alternatives to verible
-
f4pga-arch-defs
FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
-
SaaSHub
SaaSHub - Software Alternatives and Reviews. SaaSHub helps you find the best software and product alternatives
-
-
-
-
-
Surelog
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
-
Surelog
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX (by chipsalliance)
-
-
-
NOTE:
The number of mentions on this list indicates mentions on common posts plus user suggested alternatives.
Hence, a higher number means a better verible alternative or higher similarity.
verible discussion
verible reviews and mentions
Posts with mentions or reviews of verible.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-02-05.
-
How to instance module with auto-completion for verilog in neovim?
I want to write Verilog/SystemVerilog with neovim(I use Lazyvim,nvim-lspconfig,mason.nvim, mason-lspconfig.nvim and nvim-cmp) . Now I use Verible to format and lint. But it seems that it cannot complete the signals when I want to instance a module and type a "." . So is there a better way to interconnect modules?
-
Verilog LRM syntax rules
BTW, I'd recommend checking out verible if you're looking for a flex/bison verilog parser.
-
Reliable Verilog dependency analysis
You'll have to roll up your sleeves a bit, but Verible might be worth a look for a functional SystemVerilog parser that you could build off of. It's the only thing I'm aware of built for this class of tools (e.g. yosys is only synthesizable verilog) that's available and likely to cover a good amount of the spec.
-
Tools like Scitools Understand but support Verilog
https://github.com/chipsalliance/verible (may not do actual syntax checking)
-
Forking rustfmt for another language
You might be interested in this though.
-
A note from our sponsor - SaaSHub
www.saashub.com | 15 Jan 2025
Stats
Basic verible repo stats
6
1,420
9.3
9 days ago
chipsalliance/verible is an open source project licensed under GNU General Public License v3.0 or later which is an OSI approved license.
The primary programming language of verible is C++.
Sponsored
SaaSHub - Software Alternatives and Reviews
SaaSHub helps you find the best software and product alternatives
www.saashub.com