C++ systemverilog-parser Projects
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verible
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
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hdlConvertor
Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
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InfluxDB
Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.
Project mention: How to instance module with auto-completion for verilog in neovim? | /r/neovim | 2023-08-25I want to write Verilog/SystemVerilog with neovim(I use Lazyvim,nvim-lspconfig,mason.nvim, mason-lspconfig.nvim and nvim-cmp) . Now I use Verible to format and lint. But it seems that it cannot complete the signals when I want to instance a module and type a "." . So is there a better way to interconnect modules?
NOTE:
The open source projects on this list are ordered by number of github stars.
The number of mentions indicates repo mentiontions in the last 12 Months or
since we started tracking (Dec 2020).
Index
| Project | Stars | |
|---|---|---|
| 1 | verible | 1,189 |
| 2 | hdlConvertor | 266 |
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