C++ Systemverilog

Open-source C++ projects categorized as Systemverilog
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Topics: Verilog Parser systemverilog-parser Linter HacktoberFest
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Top 4 C++ Systemverilog Projects

  • verible

    Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

    • Project mention: How to instance module with auto-completion for verilog in neovim? | /r/neovim | 2023-08-25

    I want to write Verilog/SystemVerilog with neovim(I use Lazyvim,nvim-lspconfig,mason.nvim, mason-lspconfig.nvim and nvim-cmp) . Now I use Verible to format and lint. But it seems that it cannot complete the signals when I want to instance a module and type a "." . So is there a better way to interconnect modules?

  • slang

    SystemVerilog compiler and language services (by MikePopoloski)

  • InfluxDB

    Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.

    InfluxDB logo

  • Surelog

    SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX (by chipsalliance)

  • hdlConvertor

    Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4

NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020).

C++ Systemverilog related posts

  • How to instance module with auto-completion for verilog in neovim?

    1 project | /r/neovim | 25 Aug 2023

  • Is anyone aware of a commercial parser that converts modern system verilog, UVM, etc to JSON or YAML?

    1 project | /r/Verilog | 8 Jul 2022

  • Verilog LRM syntax rules

    1 project | /r/Compilers | 24 Mar 2022

  • Reliable Verilog dependency analysis

    3 projects | /r/FPGA | 5 Feb 2022

  • svls VS verible - a user suggested alternative

    2 projects | 3 Nov 2021

  • Tools like Scitools Understand but support Verilog

    4 projects | /r/FPGA | 19 Sep 2021

  • Forking rustfmt for another language

    1 project | /r/rust | 19 Feb 2021
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Index

What are some of the best open-source Systemverilog projects in C++? This list will help you:

Project Stars
1 verible 1,197
2 slang 535
3 Surelog 330
4 hdlConvertor 266

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