fusesoc VS edalize

Compare fusesoc vs edalize and see what are their differences.

fusesoc

Package manager and build abstraction tool for FPGA/ASIC development (by olofk)
Python eda Reuse package-manager Fpga Verilog Vhdl
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edalize

An abstraction library for interfacing EDA tools (by olofk)
eda Fpga fossi Xilinx altera lattice yosys Synthesis Simulation Verilog Vhdl Systemverilog Verilator icarus-verilog modelsim riviera-pro ghdl icestorm spyglass vivado
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fusesoc edalize
12 4
1,115 590
- -
7.6 7.3
13 days ago 7 days ago
Python Python
BSD 2-clause "Simplified" License BSD 2-clause "Simplified" License
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fusesoc

Posts with mentions or reviews of fusesoc. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2024-03-28.

edalize

Posts with mentions or reviews of edalize. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-02-06.
  • Dropping EDA-GUI's 101
    1 project | /r/FPGA | 17 Feb 2023
    Check out FuseSoC: https://github.com/olofk/fusesoc which can handle Vivado builds for you (utilizing edalize: https://github.com/olofk/edalize) along with some nice package management. It can run against multiple tools so you can also get it to build simulations using Verilator or a commercial EDA tool if you have access to them.
  • Introduction to FPGAs
    9 projects | news.ycombinator.com | 6 Feb 2023
    Check out https://github.com/olofk/fusesoc. It gives you a command line build flow that can drive Vivado (along with many other eda tools via edalize https://github.com/olofk/edalize) without having to touch the GUI (though you might want it for programming the board, though FuseSoC can do that too).
  • Compiling Code into Silicon
    10 projects | news.ycombinator.com | 7 Dec 2021
    This reminds me very much of edalize[1], which does something very similar.

    [1]: https://github.com/olofk/edalize

  • Olof Kindgren on LinkedIn: We have a new world record! 6000 RISC-V cores in a single chip!
    3 projects | /r/RISCV | 24 Sep 2021

What are some alternatives?

When comparing fusesoc and edalize you can also consider the following projects:

litex - Build your hardware, easily!

skywater-pdk - Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

opentitan - OpenTitan: Open source silicon root of trust

apio - :seedling: Open source ecosystem for open FPGA boards

cocotb - cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

freepdk-45nm - ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen

teroshdl-documenter-demo - This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI workflow.

icestudio - :snowflake: Visual editor for open FPGA boards

rocket-chip - Rocket Chip Generator

rggen - Code generation tool for control and status registers

vcdvcd - Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.

sphinx-vhdl

fusesoc vs litex edalize vs skywater-pdk fusesoc vs opentitan edalize vs apio fusesoc vs cocotb edalize vs freepdk-45nm fusesoc vs teroshdl-documenter-demo edalize vs icestudio fusesoc vs rocket-chip edalize vs rggen fusesoc vs vcdvcd edalize vs sphinx-vhdl