axi
Pyverilog
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axi | Pyverilog | |
---|---|---|
3 | 2 | |
922 | 571 | |
4.9% | 3.7% | |
6.8 | 0.0 | |
about 1 month ago | 9 months ago | |
SystemVerilog | Python | |
GNU General Public License v3.0 or later | Apache License 2.0 |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
axi
- AXI InterConnect
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Any recommendations for an RTL "standard library"?
Hi, I’m one of the developers of basejump. It’s pretty awesome, especially if you’re targeting ASIC. Nearly all the components have been through multiple advanced node tapeouts. The only weakness I see is a lack of AXI components. So I may suggest https://github.com/pulp-platform/axi to supplement
- How to compare HDL simulation/implementation results to Matlab?
Pyverilog
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Tools for designing hardware in Python
Any hardware designers here who use Python for designing hardware? There are a bunch of libraries that all seem promising MyHDL, PyRTL, PyVerilog, PyLog, PyMTL3, ... All seem to work roughly the same. Write code in Python and transpile it to VHDL/Verilog. Which of these are popular and well-maintained? MyHDL looks good but it's last release was 0.10 in 2018 and for hardware design you don't want to rely on 0.x software. Anything like Chisel for Python.
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How to compare HDL simulation/implementation results to Matlab?
PyVerilog https://github.com/PyHDI/Pyverilog
What are some alternatives?
chisel - Chisel: A Modern Hardware Design Language
pyverilator - Python wrapper for verilator model
nmigen - A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen
myhdl - The MyHDL development repository
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development
PyRTL - A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Simplicity, usability, clarity, and extendability rather than performance or optimization is the overarching goal.
opentitan - OpenTitan: Open source silicon root of trust
datamodel-code-generator - Pydantic model and dataclasses.dataclass generator for easy conversion of JSON, OpenAPI, JSON Schema, and YAML data sources.
qemu - Xilinx's fork of Quick EMUlator (QEMU) with improved support and modelling for the Xilinx platforms.
Cores-VeeR-EL2 - VeeR EL2 Core
nngen - NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network