Pyverilog Alternatives

Similar projects and alternatives to Pyverilog

  • pyverilator

    Python wrapper for verilator model

  • datamodel-code-generator

    Pydantic model generator for easy conversion of JSON, OpenAPI, JSON Schema, and YAML data sources.

  • SonarQube

    Static code analysis for 29 languages.. Your projects are multi-language. So is SonarQube analysis. Find Bugs, Vulnerabilities, Security Hotspots, and Code Smells so you can release quality code every time. Get started analyzing your projects today for free.

  • myhdl

    Pyverilog VS myhdl

    The MyHDL development repository

  • nmigen

    Pyverilog VS nmigen

    A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen

  • qemu

    Xilinx's fork of Quick EMUlator (QEMU) with improved support and modelling for the Xilinx platforms. (by Xilinx)

  • PyRTL

    Pyverilog VS PyRTL

    A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Simplicity, usability, clarity, and extendability rather than performance or optimization is the overarching goal.

  • pymtl3

    Pyverilog VS pymtl3

    Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework

  • Scout APM

    Less time debugging, more time building. Scout APM allows you to find and fix performance issues with no hassle. Now with error monitoring and external services monitoring, Scout is a developer's best friend when it comes to application development.

  • axi

    Pyverilog VS axi

    AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

  • pylog

    Pyverilog VS pylog

    PyLog: An Algorithm-Centric FPGA Programming and Synthesis Flow

  • PyChip-py-hcl

    A Hardware Construct Language

NOTE: The number of mentions on this list indicates mentions on common posts plus user suggested alternatives. Hence, a higher number means a better Pyverilog alternative or higher similarity.

Suggest an alternative to Pyverilog

Pyverilog reviews and mentions

Posts with mentions or reviews of Pyverilog. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-03-26.
  • Tools for designing hardware in Python
    6 projects | reddit.com/r/Python | 26 Mar 2022
    Any hardware designers here who use Python for designing hardware? There are a bunch of libraries that all seem promising MyHDL, PyRTL, PyVerilog, PyLog, PyMTL3, ... All seem to work roughly the same. Write code in Python and transpile it to VHDL/Verilog. Which of these are popular and well-maintained? MyHDL looks good but it's last release was 0.10 in 2018 and for hardware design you don't want to rely on 0.x software. Anything like Chisel for Python.
  • How to compare HDL simulation/implementation results to Matlab?
    6 projects | reddit.com/r/FPGA | 1 Jun 2021
    PyVerilog https://github.com/PyHDI/Pyverilog

Stats

Basic Pyverilog repo stats
2
383
1.3
22 days ago

PyHDI/Pyverilog is an open source project licensed under Apache License 2.0 which is an OSI approved license.

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