Pyverilog

Python-based Hardware Design Processing Toolkit for Verilog HDL (by PyHDI)
Review verilog-hdl Hardware Compiler Parser dataflow-analyzer control-flow-analyzer Code-Generator Python
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PyHDI
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    AppSignal logo

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NOTE: The number of mentions on this list indicates mentions on common posts plus user suggested alternatives. Hence, a higher number means a better Pyverilog alternative or higher similarity.
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Pyverilog reviews and mentions

Posts with mentions or reviews of Pyverilog. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-03-26.
  • Tools for designing hardware in Python
    6 projects | /r/Python | 26 Mar 2022
    Any hardware designers here who use Python for designing hardware? There are a bunch of libraries that all seem promising MyHDL, PyRTL, PyVerilog, PyLog, PyMTL3, ... All seem to work roughly the same. Write code in Python and transpile it to VHDL/Verilog. Which of these are popular and well-maintained? MyHDL looks good but it's last release was 0.10 in 2018 and for hardware design you don't want to rely on 0.x software. Anything like Chisel for Python.
  • How to compare HDL simulation/implementation results to Matlab?
    6 projects | /r/FPGA | 1 Jun 2021
    PyVerilog https://github.com/PyHDI/Pyverilog

Stats

Basic Pyverilog repo stats
2
801
0.0
over 2 years ago

PyHDI/Pyverilog is an open source project licensed under Apache License 2.0 which is an OSI approved license.

The primary programming language of Pyverilog is Python.

Popular Comparisons

  1. Pyverilog VS PyRTL
  2. Pyverilog VS nngen
  3. Pyverilog VS pyverilator
  4. Pyverilog VS nmigen
  5. Pyverilog VS pymtl3
  6. Pyverilog VS datamodel-code-generator
  7. Pyverilog VS axi
  8. Pyverilog VS myhdl
  9. Pyverilog VS pylog
  10. Pyverilog VS PyChip-py-hcl

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