Do these work as JTAG programmers?

• XilinxVirtualCable

  1 186 5.3 C

  Xilinx Virtual Cable (XVC) is a TCP/IP-based protocol that acts like a JTAG cable and provides a means to access and debug your FPGA or SoC design without using a physical cable.

  

Yes, any board with the FTDI FT232H works as a JTAG programmer (I actually have the one you linked). You may probably need some jumper wires that have the Xilinx-specific 0.2mm pitch, though, rather than the more convential 0.254mm or 0.1" pitch, if your FPGA board has the actual Xilinx JTAG header. To get it to work inside Vivado, you can use Xilinx Virtual Cable, which is a TCP/IP protocol to act as a JTAG cable (see https://github.com/Xilinx/XilinxVirtualCable and https://github.com/tmbinc/xvcd). The idea is that you basically have a TCP/IP daemon that speaks XVC and relies on libftdi or libusb to communicate with Vivado through XVC and do the actual JTAG programming.

• xvcd

  1 100 0.0 C

  Xilinx Virtual Cable Daemon

Yes, any board with the FTDI FT232H works as a JTAG programmer (I actually have the one you linked). You may probably need some jumper wires that have the Xilinx-specific 0.2mm pitch, though, rather than the more convential 0.254mm or 0.1" pitch, if your FPGA board has the actual Xilinx JTAG header. To get it to work inside Vivado, you can use Xilinx Virtual Cable, which is a TCP/IP protocol to act as a JTAG cable (see https://github.com/Xilinx/XilinxVirtualCable and https://github.com/tmbinc/xvcd). The idea is that you basically have a TCP/IP daemon that speaks XVC and relies on libftdi or libusb to communicate with Vivado through XVC and do the actual JTAG programming.

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• openFPGALoader

  13 1,044 9.2 C++

  Universal utility for programming FPGA

Alternatively, you can just use Vivado to build the bitstream and then use alternative tools like https://github.com/trabucayre/openFPGALoader and http://xc3sprog.sourceforge.net/ to upload the bitstream to your FPGA. This is what I do since I use nmigen myself.

• nmigen

  3 643 1.8 Python

  A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen

  

Alternatively, you can just use Vivado to build the bitstream and then use alternative tools like https://github.com/trabucayre/openFPGALoader and http://xc3sprog.sourceforge.net/ to upload the bitstream to your FPGA. This is what I do since I use nmigen myself.

• XVC-FTDI-JTAG

  1 41 3.2 C

  Xilinx virtual cable server for generic FTDI 4232H.

  

1) Hook up programmer to the JTAG pins of your FPGA board. If you have an actual JTAG connector then there are many variations on the pinout, but the pinout can be found at https://forums.xilinx.com/t5/FPGA-Configuration/Xilinx-JTAG-Header/td-p/909793 (for example). The advantage of the Waveshare or the HS-3 cable is that you don't have to figure out the exact connector pinout, just make sure that they match. 2) Connect the programmer using USB to your laptop/desktop/workstation. 3) Run the daemon that does XVC and handles your programmer (see the repositories I linked, and also this one: https://github.com/BerkeleyLab/XVC-FTDI-JTAG). 4) In Vivado, when adding the hardware target, you should be able to add a virtual cable with an IP address and a port. There is a button called: "Add Xilinx Virtual Cable (XVC)." Vivado then just connects to the daemon that handles the actual JTAG connection.

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