qemu
tpm2-tss
qemu | tpm2-tss | |
---|---|---|
1 | 3 | |
225 | 697 | |
1.8% | 1.4% | |
4.0 | 9.0 | |
5 days ago | 6 days ago | |
C | C | |
GNU General Public License v3.0 or later | BSD 2-clause "Simplified" License |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
qemu
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How to compare HDL simulation/implementation results to Matlab?
I'd probably simulate both the accelerator and the AXI wrapper. One could instantiate a risc-v core to drive the AXI bus under simulation. gem5 or qemu see the Xilinx fork with AXI support.
tpm2-tss
- Can Some one here verify whether it is true or false? I saw this passage on Quora. It looks Kinda funny to me.
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How to get the EK and Registration ID from a TPM 2.0 module on Raspian
If everything fails again, you may just need to build from source. I think I found what you are looking for but don't take it as set in stone - https://github.com/tpm2-software/tpm2-tss.
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TPM 2.0 through Software?
I’m just throwing this out here for those more knowledgeable than me. I was thinking that running a software TPM could be a way in which to trick Windows in to believing you have chip and would be great for those people who otherwise might nit be able to run 11 as far as we know right now. However I don’t have any idea if this would actually work or if anybody has used it in the past. https://github.com/tpm2-software/tpm2-tss
What are some alternatives?
pyverilator - Python wrapper for verilator model
tpm2-tools - The source repository for the Trusted Platform Module (TPM2.0) tools
kvm-guest-drivers-windows - Windows paravirtualized drivers for QEMU\KVM
swtpm - Libtpms-based TPM emulator with socket, character device, and Linux CUSE interface.
Pyverilog - Python-based Hardware Design Processing Toolkit for Verilog HDL
sedutil - Use sedutil for setting up and using self encrypting drives (SEDs) that comply with the TCG OPAL 2.00 standard. This includes the requisite pre-boot authentication image.
axi - AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Ventoy - A new bootable USB solution.
keyforge-burger-inserts - Keyforge Deckbox Inserts
systemd - The systemd System and Service Manager
nmigen - A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen
strongswan-docs - AsciiDoc source files for the docs.strongswan.org website