pyverilator VS axi

Compare pyverilator vs axi and see what are their differences.

pyverilator

Python wrapper for verilator model (by csail-csg)

axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication (by pulp-platform)
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pyverilator axi
1 3
70 930
- 3.0%
0.0 6.1
3 months ago 5 days ago
Python SystemVerilog
MIT License GNU General Public License v3.0 or later
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
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pyverilator

Posts with mentions or reviews of pyverilator. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2021-06-01.
  • How to compare HDL simulation/implementation results to Matlab?
    6 projects | /r/FPGA | 1 Jun 2021
    I'd use something I could drive from Python, like https://github.com/csail-csg/pyverilator and verilator since it is fast. I'd containerize the tests and use [py.test]https://docs.pytest.org/en/6.2.x/) to run specific unit or integration tests. Ideally everything would be parameterized.

axi

Posts with mentions or reviews of axi. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-06-28.

What are some alternatives?

When comparing pyverilator and axi you can also consider the following projects:

Pyverilog - Python-based Hardware Design Processing Toolkit for Verilog HDL

chisel - Chisel: A Modern Hardware Design Language

nmigen - A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen

qemu - Xilinx's fork of Quick EMUlator (QEMU) with improved support and modelling for the Xilinx platforms.

fusesoc - Package manager and build abstraction tool for FPGA/ASIC development

myhdl - The MyHDL development repository

opentitan - OpenTitan: Open source silicon root of trust

Cores-VeeR-EL2 - VeeR EL2 Core

tiny-cores - Collection of assorted small cores