pyverilator

Python wrapper for verilator model (by csail-csg)

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NOTE: The number of mentions on this list indicates mentions on common posts plus user suggested alternatives. Hence, a higher number means a better pyverilator alternative or higher similarity.

pyverilator reviews and mentions

Posts with mentions or reviews of pyverilator. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2021-06-01.
  • How to compare HDL simulation/implementation results to Matlab?
    6 projects | /r/FPGA | 1 Jun 2021
    I'd use something I could drive from Python, like https://github.com/csail-csg/pyverilator and verilator since it is fast. I'd containerize the tests and use [py.test]https://docs.pytest.org/en/6.2.x/) to run specific unit or integration tests. Ideally everything would be parameterized.

Stats

Basic pyverilator repo stats
1
70
0.0
3 months ago

csail-csg/pyverilator is an open source project licensed under MIT License which is an OSI approved license.

The primary programming language of pyverilator is Python.


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